arch/alpha/include/asm/mmu_context.h

33

register unsigned long v0 __asm__("$0");

arch/alpha/include/asm/mmu_context.h

38

: "=r"(v0), "=r"(a0)

arch/alpha/include/asm/mmu_context.h

42

return v0;

arch/alpha/include/asm/pal.h

123

register unsigned long v0 __asm__("$0");

arch/alpha/include/asm/pal.h

127

: "=r"(v0), "+r"(a0)

arch/alpha/include/asm/pal.h

131

return v0;

arch/alpha/include/asm/pal.h

137

register unsigned long v0 __asm__("$0");

arch/alpha/include/asm/pal.h

141

: "=r"(v0), "+r"(a0)

arch/alpha/include/asm/pal.h

145

return v0;

arch/alpha/include/asm/pal.h

175

register unsigned long v0 __asm__("$0");

arch/alpha/include/asm/pal.h

179

: "=r"(v0), "+r"(a0)

arch/alpha/include/asm/pal.h

183

return v0;

arch/arm64/lib/xor-neon.c

103

v0 = veorq_u64(v0, vld1q_u64(dp4 + 0));

arch/arm64/lib/xor-neon.c

109

vst1q_u64(dp1 + 0, v0);

arch/arm64/lib/xor-neon.c

133

register uint64x2_t v0, v1, v2, v3;

arch/arm64/lib/xor-neon.c

138

v0 = veorq_u64(vld1q_u64(dp1 + 0), vld1q_u64(dp2 + 0));

arch/arm64/lib/xor-neon.c

144

v0 = veorq_u64(v0, vld1q_u64(dp3 + 0));

arch/arm64/lib/xor-neon.c

150

v0 = veorq_u64(v0, vld1q_u64(dp4 + 0));

arch/arm64/lib/xor-neon.c

156

v0 = veorq_u64(v0, vld1q_u64(dp5 + 0));

arch/arm64/lib/xor-neon.c

162

vst1q_u64(dp1 + 0, v0);

arch/arm64/lib/xor-neon.c

19

register uint64x2_t v0, v1, v2, v3;

arch/arm64/lib/xor-neon.c

203

register uint64x2_t v0, v1, v2, v3;

arch/arm64/lib/xor-neon.c

208

v0 = eor3(vld1q_u64(dp1 + 0), vld1q_u64(dp2 + 0),

arch/arm64/lib/xor-neon.c

218

vst1q_u64(dp1 + 0, v0);

arch/arm64/lib/xor-neon.c

24

v0 = veorq_u64(vld1q_u64(dp1 + 0), vld1q_u64(dp2 + 0));

arch/arm64/lib/xor-neon.c

240

register uint64x2_t v0, v1, v2, v3;

arch/arm64/lib/xor-neon.c

245

v0 = eor3(vld1q_u64(dp1 + 0), vld1q_u64(dp2 + 0),

arch/arm64/lib/xor-neon.c

255

v0 = veorq_u64(v0, vld1q_u64(dp4 + 0));

arch/arm64/lib/xor-neon.c

261

vst1q_u64(dp1 + 0, v0);

arch/arm64/lib/xor-neon.c

286

register uint64x2_t v0, v1, v2, v3;

arch/arm64/lib/xor-neon.c

291

v0 = eor3(vld1q_u64(dp1 + 0), vld1q_u64(dp2 + 0),

arch/arm64/lib/xor-neon.c

30

vst1q_u64(dp1 + 0, v0);

arch/arm64/lib/xor-neon.c

301

v0 = eor3(v0, vld1q_u64(dp4 + 0), vld1q_u64(dp5 + 0));

arch/arm64/lib/xor-neon.c

307

vst1q_u64(dp1 + 0, v0);

arch/arm64/lib/xor-neon.c

48

register uint64x2_t v0, v1, v2, v3;

arch/arm64/lib/xor-neon.c

53

v0 = veorq_u64(vld1q_u64(dp1 + 0), vld1q_u64(dp2 + 0));

arch/arm64/lib/xor-neon.c

59

v0 = veorq_u64(v0, vld1q_u64(dp3 + 0));

arch/arm64/lib/xor-neon.c

65

vst1q_u64(dp1 + 0, v0);

arch/arm64/lib/xor-neon.c

86

register uint64x2_t v0, v1, v2, v3;

arch/arm64/lib/xor-neon.c

91

v0 = veorq_u64(vld1q_u64(dp1 + 0), vld1q_u64(dp2 + 0));

arch/arm64/lib/xor-neon.c

97

v0 = veorq_u64(v0, vld1q_u64(dp3 + 0));

arch/mips/cavium-octeon/octeon-irq.c

1617

u32 v0, v1;

arch/mips/cavium-octeon/octeon-irq.c

1619

r = of_property_read_u32_index(gpio_node, "interrupts", 0, &v0);

arch/mips/cavium-octeon/octeon-irq.c

1629

base_hwirq = (v0 << 6) | v1;

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

119

bne t1, v0, octeon_spin_wait_boot

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

30

dmfc0 v0, CP0_CVMMEMCTL_REG

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

32

dins v0, $0, 0, 6

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

33

ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

34

dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

35

dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

38

or v0, v0, 0x5001

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

39

xor v0, v0, 0x1001

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

43

and v0, v0, v1

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

44

ori v0, v0, (6 << 7)

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

64

or v0, v0, 0x2000 # Set IPREF bit.

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

68

dmtc0 v0, CP0_CVMCTL_REG

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

73

dli v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

74

dsll v0, 7

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

75

beqz v0, 2f

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

76

1: dsubu v0, 8

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

77

sd $0, -32768(v0)

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

78

bnez v0, 1b

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

80

mfc0 v0, CP0_PRID_REG

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

81

bbit0 v0, 15, 1f

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

83

and t1, v0, 0xff00

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

84

dli v0, 0x9500

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

85

bge t1, v0, 1f # OCTEON III has no DCACHE_ERR_REG COP0

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

86

dli v0, 0x27

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

87

dmtc0 v0, CP0_DCACHE_ERR_REG

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

90

rdhwr v0, $0

arch/mips/include/asm/mach-malta/kernel-entry-init.h

113

PTR_LA v0, 0x9fc00534 /* YAMON print */

arch/mips/include/asm/mach-malta/kernel-entry-init.h

114

lw v0, (v0)

arch/mips/include/asm/mach-malta/kernel-entry-init.h

117

jal v0

arch/mips/include/asm/mach-malta/kernel-entry-init.h

119

PTR_LA v0, 0x9fc00520 /* YAMON exit */

arch/mips/include/asm/mach-malta/kernel-entry-init.h

120

lw v0, (v0)

arch/mips/include/asm/mach-malta/kernel-entry-init.h

122

jal v0

arch/mips/include/asm/stackframe.h

255

cfi_st v0, PT_R2, \docfi

arch/mips/include/asm/stackframe.h

367

LONG_L v0, PT_STATUS(sp)

arch/mips/include/asm/stackframe.h

369

and v0, v1

arch/mips/include/asm/stackframe.h

370

or v0, a0

arch/mips/include/asm/stackframe.h

371

mtc0 v0, CP0_STATUS

arch/mips/include/asm/stackframe.h

405

LONG_L v0, PT_STATUS(sp)

arch/mips/include/asm/stackframe.h

407

and v0, v1

arch/mips/include/asm/stackframe.h

408

or v0, a0

arch/mips/include/asm/stackframe.h

409

mtc0 v0, CP0_STATUS

arch/s390/include/asm/fpu-insn-asm.h

94

.ifc \vxr,%v0

arch/x86/platform/uv/bios_uv.c

85

u64 v0, v1;

arch/x86/platform/uv/bios_uv.c

89

(u64)(&v0), (u64)(&v1), 0, 0);

arch/x86/platform/uv/bios_uv.c

93

part.val = v0;

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

643

uint32_t v0, v1, v28, v31;

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

650

v0 = REG_GET_FIELD(hw_assert_msklo,

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

659

if (v0 && v1 && v28 && v31)

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

661

else if (!v0 && !v1 && !v28 && !v31)

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

665

v0, v1, v28, v31);

drivers/gpu/drm/amd/amdgpu/df_v4_3.c

32

uint32_t v0, v1, v28, v31;

drivers/gpu/drm/amd/amdgpu/df_v4_3.c

39

v0 = REG_GET_FIELD(hw_assert_msklo,

drivers/gpu/drm/amd/amdgpu/df_v4_3.c

48

if (v0 && v1 && v28 && v31)

drivers/gpu/drm/amd/amdgpu/df_v4_3.c

50

else if (!v0 && !v1 && !v28 && !v31)

drivers/gpu/drm/amd/amdgpu/df_v4_3.c

54

v0, v1, v28, v31);

drivers/gpu/drm/nouveau/include/nvif/if000e.h

11

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0010.h

12

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0011.h

20

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0011.h

31

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

116

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

138

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

150

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

157

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

165

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

179

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

191

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

200

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

208

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

219

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

231

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

244

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

254

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

265

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

273

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

281

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

292

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

41

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

80

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

89

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

98

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0013.h

10

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0013.h

33

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0014.h

11

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0020.h

34

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0020.h

43

} v0;

drivers/gpu/drm/nouveau/include/nvif/if0021.h

14

} v0;

drivers/gpu/drm/nouveau/nvif/object.c

35

struct nvif_ioctl_v0 v0;

drivers/gpu/drm/nouveau/nvif/object.c

38

if (size >= sizeof(*args) && args->v0.version == 0) {

drivers/gpu/drm/nouveau/nvif/object.c

40

args->v0.object = nvif_handle(object);

drivers/gpu/drm/nouveau/nvif/object.c

42

args->v0.object = 0;

drivers/gpu/drm/nouveau/nvkm/core/client.c

38

struct nvif_client_v0 v0;

drivers/gpu/drm/nouveau/nvkm/core/client.c

43

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))){

drivers/gpu/drm/nouveau/nvkm/core/client.c

44

args->v0.name[sizeof(args->v0.name) - 1] = 0;

drivers/gpu/drm/nouveau/nvkm/core/client.c

45

ret = nvkm_client_new(args->v0.name, oclass->client->device, NULL,

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

103

if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

105

args->v0.version, args->v0.handle, args->v0.oclass,

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

106

args->v0.object);

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

117

oclass.handle = args->v0.handle;

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

118

oclass.object = args->v0.object;

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

124

} while (oclass.base.oclass != args->v0.oclass);

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

175

struct nvif_ioctl_mthd_v0 v0;

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

180

if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

182

args->v0.version, args->v0.method);

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

183

ret = nvkm_object_mthd(object, args->v0.method, data, size);

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

209

struct nvif_ioctl_map_v0 v0;

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

215

if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

216

nvif_ioctl(object, "map vers %d\n", args->v0.version);

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

218

&args->v0.handle,

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

219

&args->v0.length);

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

221

args->v0.type = NVIF_IOCTL_MAP_V0_IO;

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

223

args->v0.type = NVIF_IOCTL_MAP_V0_VA;

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

289

struct nvif_ioctl_v0 v0;

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

295

if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

298

args->v0.version, args->v0.type, args->v0.object,

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

299

args->v0.owner);

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

300

ret = nvkm_ioctl_path(client, args->v0.object, args->v0.type,

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

64

struct nvif_ioctl_sclass_v0 v0;

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

70

if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

72

args->v0.version, args->v0.count);

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

73

if (size != args->v0.count * sizeof(args->v0.oclass[0]))

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

77

if (i < args->v0.count) {

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

78

args->v0.oclass[i].oclass = oclass.base.oclass;

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

79

args->v0.oclass[i].minver = oclass.base.minver;

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

80

args->v0.oclass[i].maxver = oclass.base.maxver;

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

85

args->v0.count = i;

drivers/gpu/drm/nouveau/nvkm/core/ioctl.c

96

struct nvif_ioctl_new_v0 v0;

drivers/gpu/drm/nouveau/nvkm/core/uevent.c

144

if (argc < sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/core/uevent.c

154

uevent->wait = args->v0.wait;

drivers/gpu/drm/nouveau/nvkm/core/uevent.c

156

return parent->func->uevent(parent, &args->v0.data, argc - sizeof(args->v0), uevent);

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

105

if (args->v0.state != NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT) {

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

107

if (i++ == args->v0.state)

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

118

args->v0.state = pstate->pstate;

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

124

snprintf(args->v0.name, sizeof(args->v0.name), "%s", domain->mname);

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

125

snprintf(args->v0.unit, sizeof(args->v0.unit), "MHz");

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

126

args->v0.min = lo / domain->mdiv;

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

127

args->v0.max = hi / domain->mdiv;

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

129

args->v0.index = 0;

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

132

args->v0.index = ++j;

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

144

struct nvif_control_pstate_user_v0 v0;

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

150

if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

153

args->v0.version, args->v0.ustate, args->v0.pwrsrc);

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

159

if (args->v0.pwrsrc >= 0) {

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

160

ret |= nvkm_clk_ustate(clk, args->v0.ustate, args->v0.pwrsrc);

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

162

ret |= nvkm_clk_ustate(clk, args->v0.ustate, 0);

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

163

ret |= nvkm_clk_ustate(clk, args->v0.ustate, 1);

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

38

struct nvif_control_pstate_info_v0 v0;

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

44

if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

46

args->v0.version);

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

51

args->v0.count = clk->state_nr;

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

52

args->v0.ustate_ac = clk->ustate_ac;

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

53

args->v0.ustate_dc = clk->ustate_dc;

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

54

args->v0.pwrsrc = clk->pwrsrc;

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

55

args->v0.pstate = clk->pstate;

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

57

args->v0.count = 0;

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

58

args->v0.ustate_ac = NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE;

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

59

args->v0.ustate_dc = NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE;

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

60

args->v0.pwrsrc = -ENODEV;

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

61

args->v0.pstate = NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN;

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

71

struct nvif_control_pstate_attr_v0 v0;

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

82

if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

85

args->v0.version, args->v0.state, args->v0.index);

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

88

if (args->v0.state < NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT)

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

90

if (args->v0.state >= clk->state_nr)

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

97

if (domain->mname && ++j == args->v0.index)

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

112

args->v0.platform = NV_DEVICE_INFO_V0_IGP;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

117

args->v0.platform = NV_DEVICE_INFO_V0_PCI;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

120

args->v0.platform = NV_DEVICE_INFO_V0_AGP;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

123

args->v0.platform = NV_DEVICE_INFO_V0_PCIE;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

126

args->v0.platform = NV_DEVICE_INFO_V0_SOC;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

136

case NV_04: args->v0.family = NV_DEVICE_INFO_V0_TNT; break;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

138

case NV_11: args->v0.family = NV_DEVICE_INFO_V0_CELSIUS; break;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

139

case NV_20: args->v0.family = NV_DEVICE_INFO_V0_KELVIN; break;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

140

case NV_30: args->v0.family = NV_DEVICE_INFO_V0_RANKINE; break;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

141

case NV_40: args->v0.family = NV_DEVICE_INFO_V0_CURIE; break;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

142

case NV_50: args->v0.family = NV_DEVICE_INFO_V0_TESLA; break;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

143

case NV_C0: args->v0.family = NV_DEVICE_INFO_V0_FERMI; break;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

144

case NV_E0: args->v0.family = NV_DEVICE_INFO_V0_KEPLER; break;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

145

case GM100: args->v0.family = NV_DEVICE_INFO_V0_MAXWELL; break;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

146

case GP100: args->v0.family = NV_DEVICE_INFO_V0_PASCAL; break;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

147

case GV100: args->v0.family = NV_DEVICE_INFO_V0_VOLTA; break;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

148

case TU100: args->v0.family = NV_DEVICE_INFO_V0_TURING; break;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

149

case GA100: args->v0.family = NV_DEVICE_INFO_V0_AMPERE; break;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

150

case AD100: args->v0.family = NV_DEVICE_INFO_V0_ADA; break;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

151

case GH100: args->v0.family = NV_DEVICE_INFO_V0_HOPPER; break;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

152

case GB10x: args->v0.family = NV_DEVICE_INFO_V0_BLACKWELL; break;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

153

case GB20x: args->v0.family = NV_DEVICE_INFO_V0_BLACKWELL; break;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

155

args->v0.family = 0;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

159

args->v0.chipset = device->chipset;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

160

args->v0.revision = device->chiprev;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

162

args->v0.ram_size = args->v0.ram_user = fb->ram->size;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

164

args->v0.ram_size = args->v0.ram_user = 0;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

165

if (imem && args->v0.ram_size > 0)

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

166

args->v0.ram_user = args->v0.ram_user - imem->reserved;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

168

snprintf(args->v0.chip, sizeof(args->v0.chip), "%s", device->chip->name);

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

169

snprintf(args->v0.name, sizeof(args->v0.name), "%s", device->name);

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

179

struct nv_device_time_v0 v0;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

184

if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

185

nvif_ioctl(object, "device time vers %d\n", args->v0.version);

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

186

args->v0.time = nvkm_timer_read(device->timer);

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

80

struct nv_device_info_v0 v0;

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

96

if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c

97

nvif_ioctl(object, "device info vers %d\n", args->v0.version);

drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.c

193

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.c

195

if (args->v0.id >= nr || !args->v0.pushbuf != !user->func->push)

drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.c

206

chan->chid.ctrl = user->ctrl + args->v0.id;

drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.c

207

chan->chid.user = user->user + args->v0.id;

drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.c

208

chan->head = args->v0.id;

drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.c

211

ret = chan->func->push(chan, args->v0.pushbuf);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

110

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

122

if (args->v0.types & NVIF_CONN_EVENT_V0_PLUG ) bits |= NVKM_DPYID_PLUG;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

123

if (args->v0.types & NVIF_CONN_EVENT_V0_UNPLUG) bits |= NVKM_DPYID_UNPLUG;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

124

if (args->v0.types & NVIF_CONN_EVENT_V0_IRQ ) bits |= NVKM_DPYID_IRQ;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

131

if (args->v0.types & NVIF_CONN_EVENT_V0_PLUG ) bits |= NVKM_I2C_PLUG;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

132

if (args->v0.types & NVIF_CONN_EVENT_V0_UNPLUG) bits |= NVKM_I2C_UNPLUG;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

133

if (args->v0.types & NVIF_CONN_EVENT_V0_IRQ ) bits |= NVKM_I2C_IRQ;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

139

if (args->v0.types & NVIF_CONN_EVENT_V0_PLUG ) bits |= NVKM_GPIO_HI;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

140

if (args->v0.types & NVIF_CONN_EVENT_V0_UNPLUG) bits |= NVKM_GPIO_LO;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

141

if (args->v0.types & NVIF_CONN_EVENT_V0_IRQ) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

177

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

181

if (cont->index == args->v0.id) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

197

case DCB_CONNECTOR_VGA : args->v0.type = NVIF_CONN_V0_VGA; break;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

209

case DCB_CONNECTOR_TV_3 : args->v0.type = NVIF_CONN_V0_TV; break;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

218

case DCB_CONNECTOR_DVI_I : args->v0.type = NVIF_CONN_V0_DVI_I; break;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

220

case DCB_CONNECTOR_DVI_D : args->v0.type = NVIF_CONN_V0_DVI_D; break;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

223

case DCB_CONNECTOR_LVDS : args->v0.type = NVIF_CONN_V0_LVDS; break;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

224

case DCB_CONNECTOR_LVDS_SPWG : args->v0.type = NVIF_CONN_V0_LVDS_SPWG; break;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

231

case DCB_CONNECTOR_USB_C : args->v0.type = NVIF_CONN_V0_DP; break;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

232

case DCB_CONNECTOR_eDP : args->v0.type = NVIF_CONN_V0_EDP; break;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

237

case DCB_CONNECTOR_HDMI_C : args->v0.type = NVIF_CONN_V0_HDMI; break;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

247

args->v0.type = NVIF_CONN_V0_VGA;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

38

args.v0.version = 0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

39

args.v0.types = 0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

41

args.v0.types |= NVIF_CONN_EVENT_V0_PLUG;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

43

args.v0.types |= NVIF_CONN_EVENT_V0_UNPLUG;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

45

args.v0.types |= NVIF_CONN_EVENT_V0_IRQ;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

47

return object->client->event(token, &args, sizeof(args.v0));

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

55

args.v0.version = 0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

56

args.v0.types = 0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

58

args.v0.types |= NVIF_CONN_EVENT_V0_PLUG;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

60

args.v0.types |= NVIF_CONN_EVENT_V0_UNPLUG;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

62

args.v0.types |= NVIF_CONN_EVENT_V0_IRQ;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

64

return object->client->event(token, &args, sizeof(args.v0));

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

72

args.v0.version = 0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

73

args.v0.types = 0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

75

args.v0.types |= NVIF_CONN_EVENT_V0_PLUG;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

77

args.v0.types |= NVIF_CONN_EVENT_V0_UNPLUG;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

79

return object->client->event(token, &args, sizeof(args.v0));

drivers/gpu/drm/nouveau/nvkm/engine/disp/udisp.c

101

args->v0.conn_mask = 0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/udisp.c

103

args->v0.conn_mask |= BIT(conn->index);

drivers/gpu/drm/nouveau/nvkm/engine/disp/udisp.c

105

args->v0.outp_mask = 0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/udisp.c

107

args->v0.outp_mask |= BIT(outp->index);

drivers/gpu/drm/nouveau/nvkm/engine/disp/udisp.c

109

args->v0.head_mask = 0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/udisp.c

111

args->v0.head_mask |= BIT(head->id);

drivers/gpu/drm/nouveau/nvkm/engine/disp/udisp.c

89

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.c

113

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.c

115

if (!(head = nvkm_head_find(disp, args->v0.id)))

drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.c

50

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.c

54

args->v0.vtotal = head->arm.vtotal;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.c

55

args->v0.vblanks = head->arm.vblanks;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.c

56

args->v0.vblanke = head->arm.vblanke;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.c

57

args->v0.htotal = head->arm.htotal;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.c

58

args->v0.hblanks = head->arm.hblanks;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.c

59

args->v0.hblanke = head->arm.hblanke;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.c

65

if (!args->v0.vtotal || !args->v0.htotal)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.c

68

args->v0.time[0] = ktime_to_ns(ktime_get());

drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.c

69

head->func->rgpos(head, &args->v0.hline, &args->v0.vline);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.c

70

args->v0.time[1] = ktime_to_ns(ktime_get());

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

104

return outp->func->dp.drive(outp, args->v0.lanes, args->v0.pe, args->v0.vs);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

112

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

117

if (!args->v0.retrain) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

118

memcpy(outp->dp.dpcd, args->v0.dpcd, sizeof(outp->dp.dpcd));

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

119

outp->dp.lttprs = args->v0.lttprs;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

120

outp->dp.lt.nr = args->v0.link_nr;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

121

outp->dp.lt.bw = args->v0.link_bw / 27000;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

122

outp->dp.lt.mst = args->v0.mst;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

123

outp->dp.lt.post_adj = args->v0.post_lt_adj;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

126

return outp->func->dp.train(outp, args->v0.retrain);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

134

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

136

if (args->v0.rates > ARRAY_SIZE(outp->dp.rate))

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

139

for (int i = 0; i < args->v0.rates; i++) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

140

outp->dp.rate[i].dpcd = args->v0.rate[i].dpcd;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

141

outp->dp.rate[i].rate = args->v0.rate[i].rate;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

144

outp->dp.rates = args->v0.rates;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

157

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

162

return outp->func->dp.aux_xfer(outp, args->v0.type, args->v0.addr,

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

163

args->v0.data, &args->v0.size);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

171

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

176

return outp->func->dp.aux_pwr(outp, !!args->v0.state);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

185

if (argc < sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

187

argc -= sizeof(args->v0);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

189

if (!ior->hda || !nvkm_head_find(outp->disp, args->v0.head))

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

194

if (argc && args->v0.data[0]) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

196

ior->func->dp->audio(ior, args->v0.head, true);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

199

ior->func->hdmi->audio(ior, args->v0.head, true);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

201

ior->func->hda->hpd(ior, args->v0.head, true);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

202

ior->func->hda->eld(ior, args->v0.head, args->v0.data, argc);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

204

ior->func->hda->hpd(ior, args->v0.head, false);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

207

ior->func->dp->audio(ior, args->v0.head, false);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

210

ior->func->hdmi->audio(ior, args->v0.head, false);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

223

if (argc < sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

225

if (!nvkm_head_find(outp->disp, args->v0.head))

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

228

switch (ior->func->hdmi ? args->v0.type : 0xff) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

230

ior->func->hdmi->infoframe_avi(ior, args->v0.head, &args->v0.data, size);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

233

ior->func->hdmi->infoframe_vsi(ior, args->v0.head, &args->v0.data, size);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

248

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

251

if (!(outp->asy.head = nvkm_head_find(outp->disp, args->v0.head)))

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

255

args->v0.max_ac_packet > 0x1f ||

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

256

args->v0.rekey > 0x7f ||

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

257

(args->v0.scdc && !ior->func->hdmi->scdc))

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

260

if (!args->v0.enable) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

261

ior->func->hdmi->infoframe_avi(ior, args->v0.head, NULL, 0);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

262

ior->func->hdmi->infoframe_vsi(ior, args->v0.head, NULL, 0);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

263

ior->func->hdmi->ctrl(ior, args->v0.head, false, 0, 0);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

267

ior->func->hdmi->ctrl(ior, args->v0.head, args->v0.enable,

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

268

args->v0.max_ac_packet, args->v0.rekey);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

270

ior->func->hdmi->scdc(ior, args->v0.khz, args->v0.scdc, args->v0.scdc_scrambling,

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

271

args->v0.scdc_low_rates);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

281

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

286

outp->lvds.dual = !!args->v0.dual;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

287

outp->lvds.bpc8 = !!args->v0.bpc8;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

297

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

301

ret = outp->func->bl.set(outp, args->v0.level);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

314

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

320

args->v0.level = ret;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

350

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

352

if (outp->ior && args->v0.type <= NVIF_OUTP_ACQUIRE_V0_PIOR)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

355

switch (args->v0.type) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

361

ret = outp->func->acquire(outp, args->v0.sor.hda);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

371

args->v0.or = outp->ior->id;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

372

args->v0.link = outp->ior->asy.link;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

38

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

383

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

395

switch (args->v0.proto) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

40

if (!ior->func->dp || !ior->func->dp->vcpi || !nvkm_head_find(outp->disp, args->v0.head))

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

43

ior->func->dp->vcpi(ior, args->v0.head, args->v0.start_slot, args->v0.num_slots,

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

431

args->v0.or = ior->id;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

432

args->v0.link = ior->arm.link;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

433

args->v0.head = ffs(ior->arm.head) - 1;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

434

args->v0.proto = ior->arm.proto_evo;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

44

args->v0.pbn, args->v0.aligned_pbn);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

445

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

451

ret = outp->ior->func->sense(outp->ior, args->v0.data);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

452

args->v0.load = ret < 0 ? 0 : ret;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

467

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

472

args->v0.size = ARRAY_SIZE(args->v0.data);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

473

return outp->func->edid_get(outp, args->v0.data, &args->v0.size);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

482

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

489

case 0: args->v0.status = NVIF_OUTP_DETECT_V0_NOT_PRESENT; break;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

490

case 1: args->v0.status = NVIF_OUTP_DETECT_V0_PRESENT; break;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

492

args->v0.status = NVIF_OUTP_DETECT_V0_UNKNOWN;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

53

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

58

return outp->func->dp.mst_id_put(outp, args->v0.id);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

593

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

597

if (outt->index == args->v0.id) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

611

args->v0.type = NVIF_OUTP_V0_TYPE_DAC;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

612

args->v0.proto = NVIF_OUTP_V0_PROTO_RGB_CRT;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

613

args->v0.rgb_crt.freq_max = outp->info.crtconf.maxfreq;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

617

args->v0.type = NVIF_OUTP_V0_TYPE_SOR;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

618

args->v0.tmds.dual = (outp->info.tmdsconf.sor.link == 3);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

620

args->v0.type = NVIF_OUTP_V0_TYPE_PIOR;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

621

args->v0.tmds.dual = 0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

623

args->v0.proto = NVIF_OUTP_V0_PROTO_TMDS;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

626

args->v0.type = NVIF_OUTP_V0_TYPE_SOR;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

627

args->v0.proto = NVIF_OUTP_V0_PROTO_LVDS;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

628

args->v0.lvds.acpi_edid = outp->info.lvdsconf.use_acpi_for_edid;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

632

args->v0.type = NVIF_OUTP_V0_TYPE_SOR;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

633

args->v0.dp.aux = outp->info.i2c_index;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

635

args->v0.type = NVIF_OUTP_V0_TYPE_PIOR;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

636

args->v0.dp.aux = NVKM_I2C_AUX_EXT(outp->info.extdev);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

638

args->v0.proto = NVIF_OUTP_V0_PROTO_DP;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

639

args->v0.dp.mst = outp->dp.mst;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

640

args->v0.dp.increased_wm = outp->dp.increased_wm;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

641

args->v0.dp.link_nr = outp->info.dpconf.link_nr;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

642

args->v0.dp.link_bw = outp->info.dpconf.link_bw * 27000;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

651

args->v0.ddc = NVKM_I2C_BUS_EXT(outp->info.extdev);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

653

args->v0.ddc = outp->info.i2c_index;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

654

args->v0.heads = outp->info.heads;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

655

args->v0.conn = outp->info.connector;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

66

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

71

return outp->func->dp.mst_id_get(outp, &args->v0.id);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

81

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

84

if (!ior->func->dp || !nvkm_head_find(disp, args->v0.head))

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

89

return ior->func->dp->sst(ior, args->v0.head,

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

91

args->v0.watermark, args->v0.hblanksym, args->v0.vblanksym);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

99

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c

72

struct nv_dma_v0 v0;

drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c

84

if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {

drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c

87

args->v0.version, args->v0.target, args->v0.access,

drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c

88

args->v0.start, args->v0.limit);

drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c

89

dmaobj->target = args->v0.target;

drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c

90

dmaobj->access = args->v0.access;

drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c

91

dmaobj->start = args->v0.start;

drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c

92

dmaobj->limit = args->v0.limit;

drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c

74

struct gf100_dma_v0 v0;

drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c

94

if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c

97

args->v0.version, args->v0.priv, args->v0.kind);

drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c

98

kind = args->v0.kind;

drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c

99

user = args->v0.priv;

drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c

72

struct gf119_dma_v0 v0;

drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c

92

if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c

95

args->v0.version, args->v0.page, args->v0.kind);

drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c

96

kind = args->v0.kind;

drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c

97

page = args->v0.page;

drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c

71

struct gf119_dma_v0 v0;

drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c

91

if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c

94

args->v0.version, args->v0.page, args->v0.kind);

drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c

95

kind = args->v0.kind != 0;

drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c

96

page = args->v0.page != 0;

drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c

100

part = args->v0.part;

drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c

101

comp = args->v0.comp;

drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c

102

kind = args->v0.kind;

drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c

74

struct nv50_dma_v0 v0;

drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c

94

if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c

96

"comp %d kind %02x\n", args->v0.version,

drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c

97

args->v0.priv, args->v0.part, args->v0.comp,

drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c

98

args->v0.kind);

drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c

99

user = args->v0.priv;

drivers/gpu/drm/nouveau/nvkm/engine/fifo/ucgrp.c

102

vmm = nvkm_uvmm_search(oclass->client, args->v0.vmm);

drivers/gpu/drm/nouveau/nvkm/engine/fifo/ucgrp.c

115

ret = nvkm_cgrp_new(runl, args->v0.name, vmm, true, &ucgrp->cgrp);

drivers/gpu/drm/nouveau/nvkm/engine/fifo/ucgrp.c

120

args->v0.cgid = ucgrp->cgrp->id;

drivers/gpu/drm/nouveau/nvkm/engine/fifo/ucgrp.c

90

if (argc < sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/fifo/ucgrp.c

92

argc -= sizeof(args->v0);

drivers/gpu/drm/nouveau/nvkm/engine/fifo/ucgrp.c

94

if (args->v0.namelen != argc)

drivers/gpu/drm/nouveau/nvkm/engine/fifo/ucgrp.c

98

runl = nvkm_runl_get(fifo, args->v0.runlist, 0);

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

342

if (argc < sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

344

argc -= sizeof(args->v0);

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

346

if (args->v0.namelen != argc)

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

350

runl = nvkm_runl_get(fifo, args->v0.runlist, 0);

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

354

if (args->v0.vmm) {

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

355

vmm = nvkm_uvmm_search(oclass->client, args->v0.vmm);

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

360

if (args->v0.ctxdma) {

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

361

ctxdma = nvkm_dmaobj_search(oclass->client, args->v0.ctxdma);

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

368

if (args->v0.huserd) {

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

369

userd = nvkm_umem_search(oclass->client, args->v0.huserd);

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

386

ret = nvkm_chan_new_(fifo->func->chan.func, runl, args->v0.runq, cgrp, args->v0.name,

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

387

args->v0.priv != 0, args->v0.devm, vmm, ctxdma, args->v0.offset,

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

388

args->v0.length, userd, args->v0.ouserd, &uchan->chan);

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

396

args->v0.token = chan->func->doorbell_handle(chan);

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

398

args->v0.token = ~0;

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

400

args->v0.chid = chan->id;

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

403

case NVKM_MEM_TARGET_INST: args->v0.aper = NVIF_CHAN_V0_INST_APER_INST; break;

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

404

case NVKM_MEM_TARGET_VRAM: args->v0.aper = NVIF_CHAN_V0_INST_APER_VRAM; break;

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

405

case NVKM_MEM_TARGET_HOST: args->v0.aper = NVIF_CHAN_V0_INST_APER_HOST; break;

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

406

case NVKM_MEM_TARGET_NCOH: args->v0.aper = NVIF_CHAN_V0_INST_APER_NCOH; break;

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

413

args->v0.inst = nvkm_memory_addr(chan->inst->memory);

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

50

if (argc != sizeof(args->v0) || args->v0.version != 0)

drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c

53

switch (args->v0.type) {

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

165

struct fermi_a_zbc_color_v0 v0;

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

169

if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

170

switch (args->v0.format) {

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

190

ret = gf100_gr_zbc_color_get(gr, args->v0.format,

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

191

args->v0.ds,

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

192

args->v0.l2);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

194

args->v0.index = ret;

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

211

struct fermi_a_zbc_depth_v0 v0;

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

215

if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

216

switch (args->v0.format) {

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

218

ret = gf100_gr_zbc_depth_get(gr, args->v0.format,

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

219

args->v0.ds,

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

220

args->v0.l2);

drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c

48

struct nv04_nvsw_get_ref_v0 v0;

drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c

52

if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c

53

args->v0.ref = atomic_read(&chan->ref);

drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.c

100

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.c

101

args->v0.entries = buffer->entries;

drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.c

102

args->v0.get = buffer->get;

drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.c

103

args->v0.put = buffer->put;

drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.c

94

struct nvif_clb069_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c

211

u8 v0 = next->bios.ramcfg_11_03_c0;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c

225

ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mem.c

150

struct nvif_mem_ram_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mem.c

172

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mem.c

173

if (args->v0.dma) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mem.c

175

mem->dma = args->v0.dma;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mem.c

178

mem->sgl = args->v0.sgl;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.c

40

struct gf100_mem_map_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.c

46

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.c

47

uvmm.ro = args->v0.ro;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.c

48

uvmm.kind = args->v0.kind;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.c

74

struct gf100_mem_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.c

79

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.c

80

contig = args->v0.contig;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.c

40

struct nv50_mem_map_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.c

47

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.c

48

uvmm.ro = args->v0.ro;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.c

49

uvmm.kind = args->v0.kind;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.c

50

uvmm.comp = args->v0.comp;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.c

71

struct nv50_mem_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.c

76

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.c

77

type = args->v0.bankswz ? 0x02 : 0x01;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.c

78

contig = args->v0.contig;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c

147

struct nvif_mem_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c

154

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, true))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c

155

type = args->v0.type;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c

156

page = args->v0.page;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c

157

size = args->v0.size;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c

186

args->v0.page = nvkm_memory_page(umem->memory);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c

187

args->v0.addr = nvkm_memory_addr(umem->memory);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c

188

args->v0.size = nvkm_memory_size(umem->memory);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

110

struct nvif_mmu_kind_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

119

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, true))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

120

if (argc != args->v0.count * sizeof(*args->v0.data))

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

122

if (args->v0.count > count)

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

124

args->v0.kind_inv = kind_inv;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

125

memcpy(args->v0.data, kind, args->v0.count);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

157

struct nvif_mmu_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

167

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

168

args->v0.dmabits = mmu->dma_bits;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

169

args->v0.heap_nr = mmu->heap_nr;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

170

args->v0.type_nr = mmu->type_nr;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

171

args->v0.kind_nr = kinds;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

61

struct nvif_mmu_heap_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

66

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

67

if ((index = args->v0.index) >= mmu->heap_nr)

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

69

args->v0.size = mmu->heap[index].size;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

81

struct nvif_mmu_type_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

86

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

87

if ((index = args->v0.index) >= mmu->type_nr)

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

90

args->v0.heap = mmu->type[index].heap;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

91

args->v0.vram = !!(type & NVKM_MEM_VRAM);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

92

args->v0.host = !!(type & NVKM_MEM_HOST);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

93

args->v0.comp = !!(type & NVKM_MEM_COMP);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

94

args->v0.disp = !!(type & NVKM_MEM_DISP);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

95

args->v0.kind = !!(type & NVKM_MEM_KIND);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

96

args->v0.mappable = !!(type & NVKM_MEM_MAPPABLE);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

97

args->v0.coherent = !!(type & NVKM_MEM_COHERENT);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c

98

args->v0.uncached = !!(type & NVKM_MEM_UNCACHED);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

110

struct nvif_vmm_unmap_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

117

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

118

addr = args->v0.addr;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

155

struct nvif_vmm_map_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

163

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, true))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

164

addr = args->v0.addr;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

165

size = args->v0.size;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

166

handle = args->v0.memory;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

167

offset = args->v0.offset;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

235

struct nvif_vmm_put_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

242

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

243

addr = args->v0.addr;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

248

vma = nvkm_vmm_node_search(vmm, args->v0.addr);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

271

struct nvif_vmm_get_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

280

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

281

getref = args->v0.type == NVIF_VMM_GET_V0_PTES;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

282

mapref = args->v0.type == NVIF_VMM_GET_V0_ADDR;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

283

sparse = args->v0.sparse;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

284

page = args->v0.page;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

285

align = args->v0.align;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

286

size = args->v0.size;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

297

args->v0.addr = vma->addr;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

305

struct nvif_vmm_page_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

314

if (!(nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

315

if ((index = args->v0.index) >= nr)

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

318

args->v0.shift = page[index].shift;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

319

args->v0.sparse = !!(type & NVKM_VMM_PAGE_SPARSE);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

320

args->v0.vram = !!(type & NVKM_VMM_PAGE_VRAM);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

321

args->v0.host = !!(type & NVKM_VMM_PAGE_HOST);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

322

args->v0.comp = !!(type & NVKM_VMM_PAGE_COMP);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

465

struct nvif_vmm_raw_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

472

if ((ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, true)))

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

475

switch (args->v0.op) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

477

return nvkm_uvmm_mthd_raw_get(uvmm, &args->v0);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

479

return nvkm_uvmm_mthd_raw_put(uvmm, &args->v0);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

481

return nvkm_uvmm_mthd_raw_map(uvmm, &args->v0);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

483

return nvkm_uvmm_mthd_raw_unmap(uvmm, &args->v0);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

485

return nvkm_uvmm_mthd_raw_sparse(uvmm, &args->v0);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

49

struct nvif_vmm_pfnclr_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

538

struct nvif_vmm_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

546

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, more))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

547

managed = args->v0.type == NVIF_VMM_V0_TYPE_MANAGED;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

548

raw = args->v0.type == NVIF_VMM_V0_TYPE_RAW;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

549

addr = args->v0.addr;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

55

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

550

size = args->v0.size;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

56

addr = args->v0.addr;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

57

size = args->v0.size;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

582

args->v0.page_nr = 0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

584

args->v0.page_nr++;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

585

args->v0.addr = uvmm->vmm->start;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

586

args->v0.size = uvmm->vmm->limit;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

77

struct nvif_vmm_pfnmap_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

84

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, true))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

85

page = args->v0.page;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

86

addr = args->v0.addr;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

87

size = args->v0.size;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

88

phys = args->v0.phys;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c

89

if (argc != (size >> page) * sizeof(args->v0.phys[0]))

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c

245

struct gf100_vmm_map_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c

256

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c

257

vol = !!args->v0.vol;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c

258

ro = !!args->v0.ro;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c

259

priv = !!args->v0.priv;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c

260

kind = args->v0.kind;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c

151

struct gm200_vmm_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c

155

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c

156

switch (args->v0.bigpage) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c

430

struct gp100_vmm_map_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c

439

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c

440

vol = !!args->v0.vol;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c

441

ro = !!args->v0.ro;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c

442

priv = !!args->v0.priv;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c

443

kind = args->v0.kind;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c

504

struct gp100_vmm_fault_cancel_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c

509

if ((ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false)))

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c

515

aper = (args->v0.inst >> 8) & 3;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c

516

args->v0.inst >>= 12;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c

517

args->v0.inst |= aper << 28;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c

518

args->v0.inst |= 0x80000000;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c

521

if (nvkm_gr_ctxsw_inst(device) == args->v0.inst) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c

524

(args->v0.hub << 20) |

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c

525

(args->v0.gpc << 15) |

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c

526

(args->v0.client << 9));

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c

621

struct gp100_vmm_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c

626

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c

627

replay = args->v0.fault_replay != 0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c

232

struct nv50_vmm_map_v0 v0;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c

244

if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c

245

ro = !!args->v0.ro;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c

246

priv = !!args->v0.priv;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c

247

kind = args->v0.kind & 0x7f;

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c

248

comp = args->v0.comp & 0x03;

drivers/infiniband/hw/hfi1/tid_rdma.c

1027

void *v0, *v1, *vm1;

drivers/infiniband/hw/hfi1/tid_rdma.c

1033

v0 = page_address(pages[i]);

drivers/infiniband/hw/hfi1/tid_rdma.c

1034

trace_hfi1_tid_flow_page(flow->req->qp, flow, i, 1, 0, v0);

drivers/infiniband/hw/hfi1/tid_rdma.c

1039

if (v1 != (v0 + PAGE_SIZE)) {

drivers/infiniband/hw/hfi1/tid_rdma.c

1056

if (vm1 && v0 != (vm1 + PAGE_SIZE)) {

drivers/input/mouse/sentelic.c

295

int v0, v1, v2;

drivers/input/mouse/sentelic.c

301

if (fsp_reg_read(psmouse, FSP_REG_SN0, &v0))

drivers/input/mouse/sentelic.c

307

*sn = (v0 << 16) | (v1 << 8) | v2;

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

392

#define RKISP1_CIF_ISP_HIST_WEIGHT_SET_V10(v0, v1, v2, v3) \

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

393

(((v0) & 0x1f) | (((v1) & 0x1f) << 8) |\

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

422

#define RKISP1_CIF_ISP_HIST_WEIGHT_SET_V12(v0, v1, v2, v3) \

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

423

(((v0) & 0x3f) | (((v1) & 0x3f) << 8) |\

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

427

#define RKISP1_CIF_ISP_HIST_OFFS_SET_V12(v0, v1) \

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

428

(((v0) & 0x1fff) | (((v1) & 0x1fff) << 16))

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

429

#define RKISP1_CIF_ISP_HIST_SIZE_SET_V12(v0, v1) \

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

430

(((v0) & 0x7ff) | (((v1) & 0x7ff) << 16))

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

590

#define RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(v0, v1) \

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

591

(((v0) & 0xfff) | (((v1) & 0xfff) << 12))

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

592

#define RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(v0, v1) \

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

593

(((v0) & 0x1fff) | (((v1) & 0x1fff) << 13))

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

594

#define RKISP1_CIF_ISP_LSC_SECT_SIZE(v0, v1) \

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

595

(((v0) & 0xfff) | (((v1) & 0xfff) << 16))

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

596

#define RKISP1_CIF_ISP_LSC_SECT_GRAD(v0, v1) \

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

597

(((v0) & 0xfff) | (((v1) & 0xfff) << 16))

drivers/media/usb/gspca/w996Xcf.c

358

v0 = u0 + hw_bufsize / 4,

drivers/media/usb/gspca/w996Xcf.c

359

y1 = v0 + hw_bufsize / 4,

drivers/media/usb/gspca/w996Xcf.c

373

reg_w(sd, 0x28, v0 & 0xffff); /* V buf.0, low */

drivers/media/usb/gspca/w996Xcf.c

374

reg_w(sd, 0x29, v0 >> 16); /* V buf.0, high */

drivers/net/ethernet/mellanox/mlxsw/pci_hw.h

115

#define mlxsw_pci_cqe_item_helpers(name, v0, v1, v2) \

drivers/net/ethernet/mellanox/mlxsw/pci_hw.h

121

return mlxsw_pci_cqe##v0##_##name##_get(cqe); \

drivers/net/ethernet/mellanox/mlxsw/pci_hw.h

134

mlxsw_pci_cqe##v0##_##name##_set(cqe, val); \

drivers/net/ethernet/sun/niu.c

3748

u64 v0 = lp->v0;

drivers/net/ethernet/sun/niu.c

3749

u32 tx_vec = (v0 >> 32);

drivers/net/ethernet/sun/niu.c

3750

u32 rx_vec = (v0 & 0xffffffff);

drivers/net/ethernet/sun/niu.c

3754

"%s() v0[%016llx]\n", __func__, (unsigned long long)v0);

drivers/net/ethernet/sun/niu.c

4078

u64 v0, u64 v1, u64 v2)

drivers/net/ethernet/sun/niu.c

4083

lp->v0 = v0;

drivers/net/ethernet/sun/niu.c

4098

if (!v0)

drivers/net/ethernet/sun/niu.c

4118

if ((v0 | v1) & 0x8000000000000000ULL) {

drivers/net/ethernet/sun/niu.c

4165

static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)

drivers/net/ethernet/sun/niu.c

4171

tx_vec = (v0 >> 32);

drivers/net/ethernet/sun/niu.c

4172

rx_vec = (v0 & 0xffffffff);

drivers/net/ethernet/sun/niu.c

4200

u64 v0, u64 v1, u64 v2)

drivers/net/ethernet/sun/niu.c

4203

lp->v0 = v0;

drivers/net/ethernet/sun/niu.c

4206

__niu_fastpath_interrupt(np, lp->ldg_num, v0);

drivers/net/ethernet/sun/niu.c

4217

u64 v0, v1, v2;

drivers/net/ethernet/sun/niu.c

4225

v0 = nr64(LDSV0(ldg));

drivers/net/ethernet/sun/niu.c

4231

(unsigned long long) v0,

drivers/net/ethernet/sun/niu.c

4235

if (unlikely(!v0 && !v1 && !v2)) {

drivers/net/ethernet/sun/niu.c

4240

if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {

drivers/net/ethernet/sun/niu.c

4241

int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);

drivers/net/ethernet/sun/niu.c

4245

if (likely(v0 & ~((u64)1 << LDN_MIF)))

drivers/net/ethernet/sun/niu.c

4246

niu_schedule_napi(np, lp, v0, v1, v2);

drivers/net/ethernet/sun/niu.h

3178

u64 v0, v1, v2;

drivers/net/gtp.c

157

pdp->u.v0.tid == tid)

drivers/net/gtp.c

1780

pctx->u.v0.tid = nla_get_u64(info->attrs[GTPA_TID]);

drivers/net/gtp.c

1781

pctx->u.v0.flow = nla_get_u16(info->attrs[GTPA_FLOW]);

drivers/net/gtp.c

1911

pctx->u.v0.tid, pctx);

drivers/net/gtp.c

1962

hash_tid = gtp0_hashfn(pctx->u.v0.tid) % gtp->hash_size;

drivers/net/gtp.c

1975

pctx->u.v0.tid, &pctx->peer.addr,

drivers/net/gtp.c

2146

pctx->u.v0.tid, pctx);

drivers/net/gtp.c

2198

if (nla_put_u64_64bit(skb, GTPA_TID, pctx->u.v0.tid, GTPA_PAD) ||

drivers/net/gtp.c

2199

nla_put_u16(skb, GTPA_FLOW, pctx->u.v0.flow))

drivers/net/gtp.c

48

} v0;

drivers/net/gtp.c

960

gtp0->flow = htons(pctx->u.v0.flow);

drivers/net/gtp.c

963

gtp0->tid = cpu_to_be64(pctx->u.v0.tid);

drivers/net/ieee802154/mac802154_hwsim.c

582

u32 v0, v1;

drivers/net/ieee802154/mac802154_hwsim.c

594

v0 = nla_get_u32(info->attrs[MAC802154_HWSIM_ATTR_RADIO_ID]);

drivers/net/ieee802154/mac802154_hwsim.c

597

if (v0 == v1)

drivers/net/ieee802154/mac802154_hwsim.c

601

phy_v0 = hwsim_get_radio_by_id(v0);

drivers/net/ieee802154/mac802154_hwsim.c

644

u32 v0, v1;

drivers/net/ieee802154/mac802154_hwsim.c

656

v0 = nla_get_u32(info->attrs[MAC802154_HWSIM_ATTR_RADIO_ID]);

drivers/net/ieee802154/mac802154_hwsim.c

660

phy_v0 = hwsim_get_radio_by_id(v0);

drivers/net/ieee802154/mac802154_hwsim.c

691

u32 v0, v1;

drivers/net/ieee802154/mac802154_hwsim.c

705

v0 = nla_get_u32(info->attrs[MAC802154_HWSIM_ATTR_RADIO_ID]);

drivers/net/ieee802154/mac802154_hwsim.c

710

phy_v0 = hwsim_get_radio_by_id(v0);

drivers/net/wireless/broadcom/b43/main.c

1335

u32 v0, v1;

drivers/net/wireless/broadcom/b43/main.c

1340

v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);

drivers/net/wireless/broadcom/b43/main.c

1341

if (!(v0 & 0x00000001))

drivers/net/wireless/broadcom/b43/main.c

1345

stat.cookie = (v0 >> 16);

drivers/net/wireless/broadcom/b43/main.c

1348

tmp = (v0 & 0x0000FFFF);

drivers/net/wireless/broadcom/b43legacy/main.c

415

u16 v0;

drivers/net/wireless/broadcom/b43legacy/main.c

427

v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);

drivers/net/wireless/broadcom/b43legacy/main.c

442

*tsf |= v0;

drivers/net/wireless/broadcom/b43legacy/main.c

480

u16 v0 = (tsf & 0x000000000000FFFFULL);

drivers/net/wireless/broadcom/b43legacy/main.c

489

b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);

drivers/net/wireless/broadcom/b43legacy/main.c

706

u32 v0;

drivers/net/wireless/broadcom/b43legacy/main.c

712

v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);

drivers/net/wireless/broadcom/b43legacy/main.c

713

if (!(v0 & 0x00000001))

drivers/net/wireless/broadcom/b43legacy/main.c

717

stat.cookie = (v0 >> 16);

drivers/net/wireless/broadcom/b43legacy/main.c

720

tmp = (v0 & 0x0000FFFF);

drivers/net/wireless/broadcom/b43legacy/phy.c

1756

s8 v0;

drivers/net/wireless/broadcom/b43legacy/phy.c

1783

v0 = (s8)(tmp & 0x00FF);

drivers/net/wireless/broadcom/b43legacy/phy.c

1790

if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F || v3 == 0x7F) {

drivers/net/wireless/broadcom/b43legacy/phy.c

1793

v0 = (s8)(tmp & 0x00FF);

drivers/net/wireless/broadcom/b43legacy/phy.c

1799

if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F || v3 == 0x7F)

drivers/net/wireless/broadcom/b43legacy/phy.c

1801

v0 = (v0 + 0x20) & 0x3F;

drivers/net/wireless/broadcom/b43legacy/phy.c

1809

average = (v0 + v1 + v2 + v3 + 2) / 4;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

21241

u16 v0 = 0x211, v1 = 0x222, v2 = 0x144, v3 = 0x188;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

21248

1, 0x02, 16, &v0);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

21259

1, 0x12, 16, &v0);

drivers/net/wireless/mediatek/mt76/mt7615/mac.c

414

u32 v0 = le32_to_cpu(rxd[0]);

drivers/net/wireless/mediatek/mt76/mt7615/mac.c

417

fc = cpu_to_le16(FIELD_GET(MT_RXD4_FRAME_CONTROL, v0));

drivers/net/wireless/mediatek/mt76/mt76_connac_mac.c

1035

u32 v0, v2;

drivers/net/wireless/mediatek/mt76/mt76_connac_mac.c

1040

v0 = le32_to_cpu(rxv[0]);

drivers/net/wireless/mediatek/mt76/mt76_connac_mac.c

1043

idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0);

drivers/net/wireless/mediatek/mt76/mt76_connac_mac.c

1044

nss = FIELD_GET(MT_PRXV_NSTS, v0) + 1;

drivers/net/wireless/mediatek/mt76/mt76_connac_mac.c

1047

stbc = FIELD_GET(MT_PRXV_HT_STBC, v0);

drivers/net/wireless/mediatek/mt76/mt76_connac_mac.c

1048

gi = FIELD_GET(MT_PRXV_HT_SGI, v0);

drivers/net/wireless/mediatek/mt76/mt76_connac_mac.c

1049

*mode = FIELD_GET(MT_PRXV_TX_MODE, v0);

drivers/net/wireless/mediatek/mt76/mt76_connac_mac.c

1053

dcm = FIELD_GET(MT_PRXV_DCM, v0);

drivers/net/wireless/mediatek/mt76/mt76_connac_mac.c

1054

bw = FIELD_GET(MT_PRXV_FRAME_MODE, v0);

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

372

u32 v0 = le32_to_cpu(rxd[0]);

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

375

fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0));

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

439

u32 v0, v1;

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

447

v0 = le32_to_cpu(rxv[0]);

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

450

if (v0 & MT_PRXV_HT_AD_CODE)

drivers/net/wireless/mediatek/mt76/mt7921/mac.c

263

u32 v0 = le32_to_cpu(rxd[0]);

drivers/net/wireless/mediatek/mt76/mt7921/mac.c

266

fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0));

drivers/net/wireless/mediatek/mt76/mt7921/mac.c

330

u32 v0, v1;

drivers/net/wireless/mediatek/mt76/mt7921/mac.c

338

v0 = le32_to_cpu(rxv[0]);

drivers/net/wireless/mediatek/mt76/mt7921/mac.c

341

if (v0 & MT_PRXV_HT_AD_CODE)

drivers/net/wireless/mediatek/mt76/mt7925/mac.c

254

u32 v0, v2;

drivers/net/wireless/mediatek/mt76/mt7925/mac.c

259

v0 = le32_to_cpu(rxv[0]);

drivers/net/wireless/mediatek/mt76/mt7925/mac.c

262

idx = FIELD_GET(MT_PRXV_TX_RATE, v0);

drivers/net/wireless/mediatek/mt76/mt7925/mac.c

264

nss = FIELD_GET(MT_PRXV_NSTS, v0) + 1;

drivers/net/wireless/mediatek/mt76/mt7925/mac.c

443

u32 v0 = le32_to_cpu(rxd[0]);

drivers/net/wireless/mediatek/mt76/mt7925/mac.c

447

fc = cpu_to_le16(FIELD_GET(MT_RXD8_FRAME_CONTROL, v0));

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

318

u32 v0, v2;

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

323

v0 = le32_to_cpu(rxv[0]);

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

326

idx = FIELD_GET(MT_PRXV_TX_RATE, v0);

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

328

nss = FIELD_GET(MT_PRXV_NSTS, v0) + 1;

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

550

u32 v0 = le32_to_cpu(rxd[0]);

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

553

fc = cpu_to_le16(FIELD_GET(MT_RXD8_FRAME_CONTROL, v0));

drivers/net/wireless/realtek/rtw89/cam.h

34

struct rtw89_h2c_addr_cam_v0 v0;

drivers/net/wireless/realtek/rtw89/fw.c

731

const struct rtw89_fw_hdr *v0 = (const struct rtw89_fw_hdr *)fw_suit->data;

drivers/net/wireless/realtek/rtw89/fw.c

738

fw_suit->hdr_ver = le32_get_bits(v0->w3, FW_HDR_W3_HDR_VER);

drivers/net/wireless/realtek/rtw89/fw.c

742

rtw89_fw_update_ver_v0(rtwdev, fw_suit, v0);

drivers/net/wireless/realtek/rtw89/fw.c

7531

struct rtw89_h2c_rf_rxdck_v0 *v0;

drivers/net/wireless/realtek/rtw89/fw.c

7539

len = sizeof(*v0);

drivers/net/wireless/realtek/rtw89/fw.c

7549

v0 = (struct rtw89_h2c_rf_rxdck_v0 *)skb->data;

drivers/net/wireless/realtek/rtw89/fw.c

7551

v0->len = len;

drivers/net/wireless/realtek/rtw89/fw.c

7552

v0->phy = phy_idx;

drivers/net/wireless/realtek/rtw89/fw.c

7553

v0->is_afe = false;

drivers/net/wireless/realtek/rtw89/fw.c

7554

v0->kpath = RF_AB;

drivers/net/wireless/realtek/rtw89/fw.c

7555

v0->cur_band = chan->band_type;

drivers/net/wireless/realtek/rtw89/fw.c

7556

v0->cur_bw = chan->band_width;

drivers/net/wireless/realtek/rtw89/fw.c

7557

v0->cur_ch = chan->channel;

drivers/net/wireless/realtek/rtw89/fw.c

7558

v0->rxdck_dbg_en = rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK);

drivers/net/wireless/realtek/rtw89/fw.h

464

struct rtw89_h2c_ra v0;

drivers/net/wireless/realtek/rtw89/fw.h

4936

struct rtw89_h2c_rf_rxdck_v0 v0;

drivers/soc/mediatek/mtk-svs.c

924

static u32 interpolate(u32 f0, u32 f1, u32 v0, u32 v1, u32 fx)

drivers/soc/mediatek/mtk-svs.c

928

if (v0 == v1 || f0 == f1)

drivers/soc/mediatek/mtk-svs.c

929

return v0;

drivers/soc/mediatek/mtk-svs.c

932

vx = (v0 * 100) - ((((v0 - v1) * 100) / (f0 - f1)) * (f0 - fx));

drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.c

141

s32 alpha_v0 = compute_alpha(from->sigma.v0);

drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.c

149

s32 coring_v0 = compute_coring(from->coring.v0);

drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.c

161

to->alpha.v0 = alpha_v0;

drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.c

168

to->coring.v0 = coring_v0;

drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3_param.h

35

s32 v0;

drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3_param.h

45

s32 v0;

drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3_types.h

45

int v0; /** Sigma for V range similarity in dark area */

drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3_types.h

60

int v0; /** Coring threshold of V channel in dark area */

drivers/staging/media/ipu3/include/uapi/intel-ipu3.h

2628

__u32 v0;

drivers/staging/media/ipu3/include/uapi/intel-ipu3.h

2645

__u32 v0;

drivers/staging/media/ipu3/ipu3-css-params.c

2865

xnr_dmem->alpha.v0 = 2047;

fs/adfs/map.c

262

unsigned int v0, v1, v2, v3;

fs/adfs/map.c

265

v0 = v1 = v2 = v3 = 0;

fs/adfs/map.c

267

v0 += map[i] + (v3 >> 8);

fs/adfs/map.c

269

v1 += map[i + 1] + (v0 >> 8);

fs/adfs/map.c

270

v0 &= 0xff;

fs/adfs/map.c

276

v0 += v3 >> 8;

fs/adfs/map.c

277

v1 += map[1] + (v0 >> 8);

fs/adfs/map.c

281

return v0 ^ v1 ^ v2 ^ v3;

fs/fuse/file.c

421

u32 v0 = v;

fs/fuse/file.c

427

v0 += ((v1 << 4 ^ v1 >> 5) + v1) ^ (sum + k[sum & 3]);

fs/fuse/file.c

429

v1 += ((v0 << 4 ^ v0 >> 5) + v0) ^ (sum + k[sum>>11 & 3]);

fs/fuse/file.c

432

return (u64) v0 + ((u64) v1 << 32);

include/crypto/aria.h

332

static inline u32 make_u32(u8 v0, u8 v1, u8 v2, u8 v3)

include/crypto/aria.h

334

return ((u32)v0 << 24) | ((u32)v1 << 16) | ((u32)v2 << 8) | ((u32)v3);

include/uapi/linux/netfilter/xt_string.h

24

} v0;

include/uapi/linux/pkt_sched.h

231

struct tc_sfq_qopt v0;

lib/atomic64_test.c

106

int v0 = 0xaaa31337;

lib/atomic64_test.c

138

INC_RETURN_FAMILY_TEST(, v0);

lib/atomic64_test.c

139

DEC_RETURN_FAMILY_TEST(, v0);

lib/atomic64_test.c

141

XCHG_FAMILY_TEST(, v0, v1);

lib/atomic64_test.c

142

CMPXCHG_FAMILY_TEST(, v0, v1, onestwos);

lib/atomic64_test.c

149

long long v0 = 0xaaa31337c001d00dLL;

lib/atomic64_test.c

157

atomic64_t v = ATOMIC64_INIT(v0);

lib/atomic64_test.c

158

long long r = v0;

lib/atomic64_test.c

190

INIT(v0);

lib/atomic64_test.c

195

INIT(v0);

lib/atomic64_test.c

200

INC_RETURN_FAMILY_TEST(64, v0);

lib/atomic64_test.c

201

DEC_RETURN_FAMILY_TEST(64, v0);

lib/atomic64_test.c

203

XCHG_FAMILY_TEST(64, v0, v1);

lib/atomic64_test.c

204

CMPXCHG_FAMILY_TEST(64, v0, v1, v2);

lib/atomic64_test.c

206

INIT(v0);

lib/atomic64_test.c

207

BUG_ON(atomic64_add_unless(&v, one, v0));

lib/atomic64_test.c

210

INIT(v0);

lib/atomic64_test.c

22

atomic##bit##_set(&v, v0); \

lib/atomic64_test.c

23

r = v0; \

lib/atomic64_test.c

46

atomic##bit##_set(&v, v0); \

lib/atomic64_test.c

47

r = v0; \

lib/atomic64_test.c

55

atomic##bit##_set(&v, v0); \

lib/atomic64_test.c

56

r = v0; \

lib/atomic64_test.c

58

BUG_ON(atomic##bit##_##op(val, &v) != v0); \

lib/siphash.c

122

v0 ^= first;

lib/siphash.c

139

v0 ^= first;

lib/siphash.c

143

v0 ^= second;

lib/siphash.c

162

v0 ^= first;

lib/siphash.c

166

v0 ^= second;

lib/siphash.c

170

v0 ^= third;

lib/siphash.c

190

v0 ^= first;

lib/siphash.c

194

v0 ^= second;

lib/siphash.c

198

v0 ^= third;

lib/siphash.c

20

#define SIPROUND SIPHASH_PERMUTATION(v0, v1, v2, v3)

lib/siphash.c

202

v0 ^= forth;

lib/siphash.c

223

v0 ^= combined;

lib/siphash.c

23

u64 v0 = SIPHASH_CONST_0; \

lib/siphash.c

239

v0 ^= b; \

lib/siphash.c

244

return (v0 ^ v1) ^ (v2 ^ v3);

lib/siphash.c

257

v0 ^= m;

lib/siphash.c

290

v0 ^= m;

lib/siphash.c

31

v0 ^= key->key[0];

lib/siphash.c

336

v0 ^= combined;

lib/siphash.c

355

v0 ^= combined;

lib/siphash.c

37

v0 ^= b; \

lib/siphash.c

376

v0 ^= combined;

lib/siphash.c

380

v0 ^= combined;

lib/siphash.c

385

#define HSIPROUND HSIPHASH_PERMUTATION(v0, v1, v2, v3)

lib/siphash.c

388

u32 v0 = HSIPHASH_CONST_0; \

lib/siphash.c

396

v0 ^= key->key[0];

lib/siphash.c

401

v0 ^= b; \

lib/siphash.c

419

v0 ^= m;

lib/siphash.c

43

return (v0 ^ v1) ^ (v2 ^ v3);

lib/siphash.c

442

v0 ^= m;

lib/siphash.c

463

v0 ^= first;

lib/siphash.c

479

v0 ^= first;

lib/siphash.c

482

v0 ^= second;

lib/siphash.c

500

v0 ^= first;

lib/siphash.c

503

v0 ^= second;

lib/siphash.c

506

v0 ^= third;

lib/siphash.c

525

v0 ^= first;

lib/siphash.c

528

v0 ^= second;

lib/siphash.c

531

v0 ^= third;

lib/siphash.c

534

v0 ^= forth;

lib/siphash.c

57

v0 ^= m;

lib/siphash.c

90

v0 ^= m;

net/sched/sch_sfq.c

838

opt.v0.quantum = q->quantum;

net/sched/sch_sfq.c

839

opt.v0.perturb_period = q->perturb_period / HZ;

net/sched/sch_sfq.c

840

opt.v0.limit = q->limit;

net/sched/sch_sfq.c

841

opt.v0.divisor = q->divisor;

net/sched/sch_sfq.c

842

opt.v0.flows = q->maxflows;

tools/include/uapi/linux/pkt_sched.h

230

struct tc_sfq_qopt v0;

tools/perf/util/demangle-rust-v0.c

1949

struct demangle_v0 v0;

tools/perf/util/demangle-rust-v0.c

1950

st = rust_demangle_v0_demangle(s, s_len, &v0, &suffix);

tools/perf/util/demangle-rust-v0.c

1954

.mangled=v0.mangled,

tools/perf/util/demangle-rust-v0.c

1955

.mangled_len=v0.mangled_len,

tools/perf/util/demangle-rust-v0.c

2022

struct demangle_v0 v0 = {

tools/perf/util/demangle-rust-v0.c

2026

if (rust_demangle_v0_display_demangle(v0, out, len, alternate) == OverflowOverflow) {

tools/testing/selftests/bpf/progs/test_siphash.h

26

#define SIPROUND SIPHASH_PERMUTATION(v0, v1, v2, v3)

tools/testing/selftests/bpf/progs/test_siphash.h

29

u64 v0 = SIPHASH_CONST_0; \

tools/testing/selftests/bpf/progs/test_siphash.h

37

v0 ^= key->key[0];

tools/testing/selftests/bpf/progs/test_siphash.h

43

v0 ^= b; \

tools/testing/selftests/bpf/progs/test_siphash.h

49

return (v0 ^ v1) ^ (v2 ^ v3);

tools/testing/selftests/bpf/progs/test_siphash.h

57

v0 ^= first;

tools/testing/selftests/bpf/progs/test_siphash.h

61

v0 ^= second;

tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c

54

CHECK_VECTOR_REGISTER(v0);