uw32
uw32(DCR1, 0x1); // Tx polling again
uw32(DCR7, 0); /* Disable Interrupt */
uw32(DCR5, ur32(DCR5));
uw32(DCR4, db->first_tx_desc_dma); /* TX DESC address */
uw32(DCR3, db->first_rx_desc_dma); /* RX DESC address */
uw32(DCR6, cr6_data);
uw32(DCR1, 0x1); /* Issue Tx polling */
uw32(DCR9, CR9_SROM_READ);
uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
uw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
uw32(DCR9, CR9_SROM_READ);
uw32(DCR10, cr10_value);
uw32(DCR10, cr10_value);
uw32(DCR9, data); /* MII Clock Low */
uw32(DCR9, data | MDCLKH); /* MII Clock High */
uw32(DCR9, data); /* MII Clock Low */
uw32(DCR9, 0x50000);
uw32(DCR9, 0x40000);
uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
uw32(DCR0, 0x10000); //Diagnosis mode
uw32(DCR13, 0x1c0); //Reset dianostic pointer port
uw32(DCR14, 0); //Clear reset port
uw32(DCR14, 0x10); //Reset ID Table pointer
uw32(DCR14, 0); //Clear reset port
uw32(DCR13, 0); //Clear CR13
uw32(DCR13, 0x1b0); //Select ID Table access port
uw32(DCR13, 0); //Clear CR13
uw32(DCR0, 0); //Clear CR0
uw32(DCR0, ULI526X_RESET); /* RESET MAC */
uw32(DCR0, db->cr0_data);
uw32(DCR7, db->cr7_data);
uw32(DCR15, db->cr15_data);
uw32(DCR7, 0);
uw32(DCR1, 0x1); /* Issue Tx polling */
uw32(DCR7, db->cr7_data);
uw32(DCR0, ULI526X_RESET);
uw32(DCR7, 0);
uw32(DCR5, db->cr5_data);
uw32(DCR7, db->cr7_data);
uw32(DCR7, db->cr7_data);