tx_control
bool tx_control;
bool tx_control = false;
tx_control = true;
ictx->tx_control = tx_control;
if (!ictx->tx_control) {
long tx_control = np->cur_tx->control;
if (!(tx_control & TXLD)) { /* this pkt is combined by two tx descriptors */
tx_control = next->control;
((tx_control & PKTSMask) >> PKTSShift);
((tx_control & PKTSMask) >> PKTSShift);
swqe->tx_control |= EHEA_SWQE_TSO;
swqe->tx_control |= EHEA_SWQE_IMM_DATA_PRESENT | EHEA_SWQE_CRC;
swqe->tx_control |= EHEA_SWQE_IP_CHECKSUM;
swqe->tx_control |= EHEA_SWQE_TCP_CHECKSUM;
swqe->tx_control |= EHEA_SWQE_TCP_CHECKSUM;
swqe->tx_control |= EHEA_SWQE_DESCRIPTORS_PRESENT;
swqe->tx_control |= EHEA_SWQE_VLAN_INSERT;
swqe->tx_control |= EHEA_SWQE_SIGNALLED_COMPLETION;
swqe->tx_control |= EHEA_SWQE_SIGNALLED_COMPLETION;
swqe->tx_control |= EHEA_SWQE_PURGE;
swqe->tx_control |= EHEA_SWQE_PURGE;
swqe->tx_control |= EHEA_SWQE_PURGE;
swqe->tx_control |= EHEA_SWQE_SIGNALLED_COMPLETION;
swqe->tx_control |= EHEA_SWQE_IMM_DATA_PRESENT;
u16 tx_control;
FALCON_DMA_STAT(tx_control, XgTxControlPkts),
SIENA_DMA_STAT(tx_control, TX_CONTROL_PKTS),
__raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
__raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
u32 tx_control[2], __res1[2]; /* 000 */
&port->regs->tx_control[0]);
&port->regs->tx_control[0]);
u16 rfatt, u16 bbatt, u16 tx_control)
u16 rfatt, u16 bbatt, u16 tx_control);
b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control);
b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control);
old_tx_control = gphy->tx_control;
const struct b43_rfatt *rfatt, u8 tx_control)
gphy->tx_control = tx_control;
gphy->rfatt.with_padmix = !!(tx_control & B43_TXCTL_TXMIX);
bb, rf, tx_control, tx_bias, tx_magn);
(rf & 0x000F) | (tx_control & 0x0070));
b43_radio_maskset(dev, 0x52, ~0x0070, (tx_control & 0x0070));
gphy->tx_control = (default_tx_control(dev) << 4);
u8 tx_control;
tx_control = gphy->tx_control;
if (tx_control == 0) {
tx_control =
} else if (rfatt > 4 && tx_control) {
tx_control = 0;
gphy->tx_control = tx_control;
gphy->tx_control);
u8 tx_control; /* B43_TXCTL_XXX */
__le32 tx_control;
txpd->tx_control |= cpu_to_le32(TxPD_MESH_FRAME);
txpd->tx_control = cpu_to_le32(convert_radiotap_rate_to_mv(rtap_hdr->rate));
__le32 tx_control;
txpd->tx_control |= cpu_to_le32(MRVL_PER_PACKET_RATE |
if (local_tx_pd->tx_control == 0)
local_tx_pd->tx_control = cpu_to_le32(priv->pkt_tx_ctrl);
u32 tx_control = 0, pkt_type = PKT_TYPE_MGMT;
memcpy(skb_push(skb, sizeof(tx_control)),
&tx_control, sizeof(tx_control));
u32 tx_control = 0, pkt_type = PKT_TYPE_MGMT;
memcpy(skb_push(skb, sizeof(tx_control)),
&tx_control, sizeof(tx_control));
__le32 tx_control;
__le32 tx_control;
if (!local_tx_pd->tx_control)
local_tx_pd->tx_control = cpu_to_le32(priv->pkt_tx_ctrl);
local_tx_pd->tx_control = cpu_to_le32(priv->pkt_tx_ctrl);
local_tx_pd->tx_control =
u32 pkt_type, tx_control;
tx_control = 0;
memcpy(pos + sizeof(pkt_type), &tx_control, sizeof(tx_control));
txpd->tx_control =
if (!txpd->tx_control)
txpd->tx_control = cpu_to_le32(priv->pkt_tx_ctrl);
struct tx_control control;