Symbol: tunnel_reg
drivers/gpu/drm/display/drm_dp_tunnel.c
243
u8 drv_id = tunnel_reg(regs, DP_USB4_DRIVER_ID) & DP_USB4_DRIVER_ID_MASK;
drivers/gpu/drm/display/drm_dp_tunnel.c
244
u8 group_id = tunnel_reg(regs, DP_IN_ADAPTER_TUNNEL_INFORMATION) & DP_GROUP_ID_MASK;
drivers/gpu/drm/display/drm_dp_tunnel.c
255
int gr = tunnel_reg(regs, DP_BW_GRANULARITY) & DP_BW_GRANULARITY_MASK;
drivers/gpu/drm/display/drm_dp_tunnel.c
265
u8 bw_code = tunnel_reg(regs, DP_TUNNELING_MAX_LINK_RATE);
drivers/gpu/drm/display/drm_dp_tunnel.c
272
return tunnel_reg(regs, DP_TUNNELING_MAX_LANE_COUNT) &
drivers/gpu/drm/display/drm_dp_tunnel.c
280
if ((tunnel_reg(regs, DP_TUNNELING_CAPABILITIES) & cap_mask) != cap_mask)
drivers/gpu/drm/display/drm_dp_tunnel.c
283
return tunnel_reg(regs, DP_USB4_DRIVER_BW_CAPABILITY) &
drivers/gpu/drm/display/drm_dp_tunnel.c
289
return tunnel_reg(regs, DP_DPTX_BW_ALLOCATION_MODE_CONTROL) &
drivers/gpu/drm/display/drm_dp_tunnel.c
490
tunnel->adapter_id = tunnel_reg(regs, DP_IN_ADAPTER_INFO) & DP_IN_ADAPTER_NUMBER_MASK;
drivers/gpu/drm/display/drm_dp_tunnel.c
498
tunnel->allocated_bw = tunnel_reg(regs, DP_ALLOCATED_BW) *
drivers/gpu/drm/display/drm_dp_tunnel.c
512
tunnel->pr_optimization_support = tunnel_reg(regs, DP_TUNNELING_CAPABILITIES) &
drivers/gpu/drm/display/drm_dp_tunnel.c
568
if (tunnel_reg(regs, DP_ALLOCATED_BW)) {
drivers/gpu/drm/display/drm_dp_tunnel.c
605
if (tunnel_reg(regs, DP_ALLOCATED_BW) > tunnel_reg(regs, DP_ESTIMATED_BW)) {
drivers/gpu/drm/display/drm_dp_tunnel.c
608
DPTUN_BW_ARG(tunnel_reg(regs, DP_ALLOCATED_BW) *
drivers/gpu/drm/display/drm_dp_tunnel.c
610
DPTUN_BW_ARG(tunnel_reg(regs, DP_ESTIMATED_BW) *
drivers/gpu/drm/display/drm_dp_tunnel.c
670
tunnel_reg(regs, DP_ALLOCATED_BW) * tunnel->bw_granularity) {
drivers/gpu/drm/display/drm_dp_tunnel.c
674
DPTUN_BW_ARG(tunnel_reg(regs, DP_ALLOCATED_BW) * tunnel->bw_granularity));
drivers/gpu/drm/display/drm_dp_tunnel.c
772
if (!(tunnel_reg(&regs, DP_TUNNELING_CAPABILITIES) &
drivers/gpu/drm/display/drm_dp_tunnel.c
790
(tunnel_reg(&regs, DP_TUNNELING_HW_REV) & DP_TUNNELING_HW_REV_MAJOR_MASK) >>
drivers/gpu/drm/display/drm_dp_tunnel.c
792
(tunnel_reg(&regs, DP_TUNNELING_HW_REV) & DP_TUNNELING_HW_REV_MINOR_MASK) >>
drivers/gpu/drm/display/drm_dp_tunnel.c
794
tunnel_reg(&regs, DP_TUNNELING_SW_REV_MAJOR),
drivers/gpu/drm/display/drm_dp_tunnel.c
795
tunnel_reg(&regs, DP_TUNNELING_SW_REV_MINOR),
drivers/gpu/drm/display/drm_dp_tunnel.c
796
str_yes_no(tunnel_reg(&regs, DP_TUNNELING_CAPABILITIES) &
drivers/gpu/drm/display/drm_dp_tunnel.c
878
tunnel->estimated_bw = tunnel_reg(regs, DP_ESTIMATED_BW) * tunnel->bw_granularity;