drivers/crypto/intel/qat/qat_common/icp_qat_fw_la.h

83

cmp_auth, ret_auth, update_state, \

drivers/crypto/intel/qat/qat_common/icp_qat_fw_la.h

97

((update_state & QAT_LA_UPDATE_STATE_MASK) << \

drivers/firmware/arm_scmi/clock.c

294

.update_state = iter_clk_possible_parents_update_state,

drivers/firmware/arm_scmi/clock.c

518

.update_state = iter_clk_describe_update_state,

drivers/firmware/arm_scmi/driver.c

1837

ret = iops->update_state(st, i->resp, i->priv);

drivers/firmware/arm_scmi/perf.c

472

.update_state = iter_perf_levels_update_state,

drivers/firmware/arm_scmi/pinctrl.c

294

.update_state = iter_pinctrl_assoc_update_state,

drivers/firmware/arm_scmi/pinctrl.c

404

.update_state = iter_pinctrl_settings_get_update_state,

drivers/firmware/arm_scmi/protocols.h

227

int (*update_state)(struct scmi_iterator_state *st,

drivers/firmware/arm_scmi/sensors.c

359

.update_state = iter_intervals_update_state,

drivers/firmware/arm_scmi/sensors.c

497

.update_state = iter_axes_extended_name_update_state,

drivers/firmware/arm_scmi/sensors.c

532

.update_state = iter_axes_desc_update_state,

drivers/firmware/arm_scmi/sensors.c

697

.update_state = iter_sens_descr_update_state,

drivers/firmware/arm_scmi/vendors/imx/imx-sm-misc.c

433

.update_state = iter_misc_syslog_update_state,

drivers/firmware/arm_scmi/voltage.c

187

.update_state = iter_volt_levels_update_state,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1004

update_state->pg_pipe_res_update[PG_OPTC][0] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1009

if (!update_state->pg_pipe_res_update[PG_HUBP][i] &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1010

!update_state->pg_pipe_res_update[PG_DPP][i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1012

update_state->pg_pipe_res_update[PG_HUBP][j] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1013

update_state->pg_pipe_res_update[PG_DPP][j] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1023

struct pg_block_update *update_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1029

memset(update_state, 0, sizeof(struct pg_block_update));

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1044

update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1047

update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1050

update_state->pg_pipe_res_update[j][new_pipe->plane_res.mpcc_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1053

update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1056

update_state->pg_pipe_res_update[j][new_pipe->stream_res.opp->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1059

update_state->pg_pipe_res_update[j][new_pipe->stream_res.tg->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1062

update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1071

update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1076

update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1081

update_state->pg_pipe_res_update[j][new_pipe->stream_res.opp->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1086

update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1091

update_state->pg_pipe_res_update[j][new_pipe->stream_res.tg->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1096

update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1103

update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1114

update_state->pg_res_update[PG_HPO] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1117

update_state->pg_pipe_res_update[PG_HDMISTREAM][0] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1124

update_state->pg_pipe_res_update[PG_DSC][new_pipe->stream_res.dsc->inst]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1125

update_state->pg_pipe_res_update[PG_HUBP][new_pipe->stream_res.dsc->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1126

update_state->pg_pipe_res_update[PG_DPP][new_pipe->stream_res.dsc->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1132

update_state->pg_pipe_res_update[PG_HUBP][j] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1133

update_state->pg_pipe_res_update[PG_DPP][j] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1140

if (update_state->pg_pipe_res_update[PG_HUBP][i] &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1141

update_state->pg_pipe_res_update[PG_DPP][i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1143

update_state->pg_pipe_res_update[PG_HUBP][j] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1144

update_state->pg_pipe_res_update[PG_DPP][j] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1177

struct pg_block_update *update_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1187

if (update_state->pg_res_update[PG_HPO]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1194

if (update_state->pg_pipe_res_update[PG_HUBP][i] &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1195

update_state->pg_pipe_res_update[PG_DPP][i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1202

if (update_state->pg_pipe_res_update[PG_DSC][i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1209

if (update_state->pg_pipe_res_update[PG_DSC][i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1214

if (update_state->pg_pipe_res_update[PG_HUBP][i] &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1215

update_state->pg_pipe_res_update[PG_DPP][i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1254

struct pg_block_update *update_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1270

if (update_state->pg_pipe_res_update[PG_DSC][i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1277

if (update_state->pg_pipe_res_update[PG_HUBP][i] &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1278

update_state->pg_pipe_res_update[PG_DPP][i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1284

if (update_state->pg_pipe_res_update[PG_DSC][i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1290

if (update_state->pg_res_update[PG_HPO]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1296

struct pg_block_update *update_state, bool power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1306

if (update_state->pg_pipe_res_update[PG_HUBP][i] &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1307

update_state->pg_pipe_res_update[PG_DPP][i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1311

if (update_state->pg_pipe_res_update[PG_DPSTREAM][i])

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1317

if (update_state->pg_pipe_res_update[PG_PHYSYMCLK][i])

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1323

if (update_state->pg_pipe_res_update[PG_DSC][i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1336

if (update_state->pg_pipe_res_update[PG_HUBP][i] &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1337

update_state->pg_pipe_res_update[PG_DPP][i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1341

if (update_state->pg_pipe_res_update[PG_DPSTREAM][i])

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1347

if (update_state->pg_pipe_res_update[PG_PHYSYMCLK][i])

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1561

static void dcn35_calc_blocks_to_ungate_for_hw_release(struct dc *dc, struct pg_block_update *update_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1565

memset(update_state, 0, sizeof(struct pg_block_update));

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1569

update_state->pg_pipe_res_update[j][i] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1571

update_state->pg_res_update[PG_HPO] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1572

update_state->pg_res_update[PG_DWB] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

919

struct pg_block_update *update_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

927

memset(update_state, 0, sizeof(struct pg_block_update));

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

938

update_state->pg_res_update[PG_HPO] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

940

update_state->pg_res_update[PG_DWB] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

946

update_state->pg_pipe_res_update[j][i] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

952

update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->plane_res.hubp->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

955

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

958

update_state->pg_pipe_res_update[PG_MPCC][pipe_ctx->plane_res.mpcc_inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

961

update_state->pg_pipe_res_update[PG_DSC][pipe_ctx->stream_res.dsc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

963

update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->stream_res.dsc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

964

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->stream_res.dsc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

970

update_state->pg_pipe_res_update[PG_HUBP][j] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

971

update_state->pg_pipe_res_update[PG_DPP][j] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

978

update_state->pg_pipe_res_update[PG_OPP][pipe_ctx->stream_res.opp->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

981

update_state->pg_pipe_res_update[PG_DPSTREAM][pipe_ctx->stream_res.hpo_dp_stream_enc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

985

update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

987

update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

994

update_state->pg_pipe_res_update[PG_OPTC][i] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

67

struct pg_block_update *update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

69

struct pg_block_update *update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

71

struct pg_block_update *update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

73

struct pg_block_update *update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

75

struct pg_block_update *update_state, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

100

struct pg_block_update *update_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

109

if (update_state->pg_pipe_res_update[PG_DSC][i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

114

if (update_state->pg_pipe_res_update[PG_HUBP][i] &&

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

115

update_state->pg_pipe_res_update[PG_DPP][i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

153

struct pg_block_update *update_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

171

if (update_state->pg_pipe_res_update[PG_HUBP][i] &&

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

172

update_state->pg_pipe_res_update[PG_DPP][i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

177

if (update_state->pg_pipe_res_update[PG_DSC][i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

39

struct pg_block_update *update_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

43

dcn35_calc_blocks_to_gate(dc, context, update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

46

if (!update_state->pg_pipe_res_update[PG_HUBP][i] &&

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

47

!update_state->pg_pipe_res_update[PG_DPP][i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

49

update_state->pg_pipe_res_update[PG_HUBP][j] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

50

update_state->pg_pipe_res_update[PG_DPP][j] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

59

struct pg_block_update *update_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

63

dcn35_calc_blocks_to_ungate(dc, context, update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

66

if (update_state->pg_pipe_res_update[PG_HUBP][i] &&

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

67

update_state->pg_pipe_res_update[PG_DPP][i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

69

update_state->pg_pipe_res_update[PG_HUBP][j] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

70

update_state->pg_pipe_res_update[PG_DPP][j] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h

33

struct pg_block_update *update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h

35

struct pg_block_update *update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h

37

struct pg_block_update *update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h

39

struct pg_block_update *update_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1239

struct pg_block_update *update_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1241

struct pg_block_update *update_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1243

struct pg_block_update *update_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1245

struct pg_block_update *update_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1247

struct pg_block_update *update_state, bool power_on);

drivers/infiniband/sw/rxe/rxe_req.c

816

update_state(qp, &pkt);

drivers/scsi/aha152x.c

2354

dataphase=update_state(shpnt);

drivers/watchdog/wm831x_wdt.c

31

int update_state;