arch/arm64/kvm/sys_regs.c

1331

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

1424

#define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }

arch/arm64/kvm/sys_regs.c

1425

#define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }

arch/arm64/kvm/sys_regs.c

1426

#define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }

arch/arm64/kvm/sys_regs.c

1427

#define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }

arch/arm64/kvm/sys_regs.c

1442

{ SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \

arch/arm64/kvm/sys_regs.c

1601

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

2519

.access = undef_access, \

arch/arm64/kvm/sys_regs.c

3140

{ SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 },

arch/arm64/kvm/sys_regs.c

3295

{ SYS_DESC(SYS_TRFCR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3296

{ SYS_DESC(SYS_SMPRI_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3297

{ SYS_DESC(SYS_SMCR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3313

{ SYS_DESC(SYS_ICC_PMR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3339

{ SYS_DESC(SYS_PMSCR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3340

{ SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3341

{ SYS_DESC(SYS_PMSICR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3342

{ SYS_DESC(SYS_PMSIRR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3343

{ SYS_DESC(SYS_PMSFCR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3344

{ SYS_DESC(SYS_PMSEVFR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3345

{ SYS_DESC(SYS_PMSLATFR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3346

{ SYS_DESC(SYS_PMSIDR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3347

{ SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3348

{ SYS_DESC(SYS_PMBPTR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3349

{ SYS_DESC(SYS_PMBSR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3350

{ SYS_DESC(SYS_PMSDSFR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3374

{ SYS_DESC(SYS_MPAMIDR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3377

{ SYS_DESC(SYS_MPAM1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3378

{ SYS_DESC(SYS_MPAM0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3382

{ SYS_DESC(SYS_ICC_IAR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3383

{ SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3384

{ SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3385

{ SYS_DESC(SYS_ICC_BPR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3386

{ SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3387

{ SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3388

{ SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3389

{ SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3390

{ SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3391

{ SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3392

{ SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3393

{ SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3395

{ SYS_DESC(SYS_ICC_RPR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3399

{ SYS_DESC(SYS_ICC_IAR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3400

{ SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3401

{ SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3402

{ SYS_DESC(SYS_ICC_BPR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3403

{ SYS_DESC(SYS_ICC_CTLR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3405

{ SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3406

{ SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3411

{ SYS_DESC(SYS_ACCDATA_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3413

{ SYS_DESC(SYS_SCXTNUM_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3428

{ SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility },

arch/arm64/kvm/sys_regs.c

3429

{ SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility },

arch/arm64/kvm/sys_regs.c

3477

{ SYS_DESC(SYS_TPIDR2_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3479

{ SYS_DESC(SYS_SCXTNUM_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3481

{ SYS_DESC(SYS_AMCR_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3482

{ SYS_DESC(SYS_AMCFGR_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3483

{ SYS_DESC(SYS_AMCGCR_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3484

{ SYS_DESC(SYS_AMUSERENR_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3485

{ SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3486

{ SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3487

{ SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3488

{ SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3669

{ SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 },

arch/arm64/kvm/sys_regs.c

3688

{ SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 },

arch/arm64/kvm/sys_regs.c

3693

{ SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 },

arch/arm64/kvm/sys_regs.c

3706

{ SYS_DESC(SYS_MPAMHCR_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3707

{ SYS_DESC(SYS_MPAMVPMV_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3708

{ SYS_DESC(SYS_MPAM2_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3709

{ SYS_DESC(SYS_MPAMVPM0_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3710

{ SYS_DESC(SYS_MPAMVPM1_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3711

{ SYS_DESC(SYS_MPAMVPM2_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3712

{ SYS_DESC(SYS_MPAMVPM3_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3713

{ SYS_DESC(SYS_MPAMVPM4_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3714

{ SYS_DESC(SYS_MPAMVPM5_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3715

{ SYS_DESC(SYS_MPAMVPM6_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3716

{ SYS_DESC(SYS_MPAMVPM7_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3719

{ SYS_DESC(SYS_RVBAR_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3720

{ SYS_DESC(SYS_RMR_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3846

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

3939

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

3964

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

4018

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

4043

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

4077

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

4458

{ CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4508

{ CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4509

{ CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4510

{ CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4511

{ CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4512

{ CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4513

{ CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4514

{ CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4515

{ CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4516

{ CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4517

{ CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4518

{ CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4519

{ CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4521

{ CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4522

{ CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4523

{ CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4524

{ CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4525

{ CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4526

{ CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4528

{ CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4529

{ CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4608

{ Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access },

arch/arm64/kvm/sys_regs.c

527

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

609

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

655

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

66

return undef_access(vcpu, params, r);

arch/arm64/kvm/sys_regs.c

674

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

677

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

707

return undef_access(vcpu, p, r);