ullong
module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);
module_param(address_space_size, ullong, 0600);
module_param_named(debug_mask, rtl88ee_mod_params.debug_mask, ullong, 0644);
module_param_named(debug_mask, rtl92ce_mod_params.debug_mask, ullong, 0644);
module_param_named(debug_mask, rtl92cu_mod_params.debug_mask, ullong, 0644);
module_param_named(debug_mask, rtl92de_mod_params.debug_mask, ullong, 0644);
module_param_named(debug_mask, rtl92du_mod_params.debug_mask, ullong, 0644);
module_param_named(debug_mask, rtl92ee_mod_params.debug_mask, ullong, 0644);
module_param_named(debug_mask, rtl92se_mod_params.debug_mask, ullong, 0644);
module_param_named(debug_mask, rtl8723e_mod_params.debug_mask, ullong, 0644);
module_param_named(debug_mask, rtl8723be_mod_params.debug_mask, ullong, 0644);
module_param_named(debug_mask, rtl8821ae_mod_params.debug_mask, ullong, 0644);
xeon_b2b_usd_addr.bar2_addr64, ullong, 0644);
xeon_b2b_usd_addr.bar4_addr64, ullong, 0644);
xeon_b2b_usd_addr.bar4_addr32, ullong, 0644);
xeon_b2b_usd_addr.bar5_addr32, ullong, 0644);
xeon_b2b_dsd_addr.bar2_addr64, ullong, 0644);
xeon_b2b_dsd_addr.bar4_addr64, ullong, 0644);
xeon_b2b_dsd_addr.bar4_addr32, ullong, 0644);
xeon_b2b_dsd_addr.bar5_addr32, ullong, 0644);
module_param_named(max_lun, max_lun, ullong, S_IRUGO);
module_param_array(lpfc_enable_nvmet, ullong, &lpfc_enable_nvmet_cnt, 0444);
module_param(lpfc_##name, ullong, S_IRUGO);\
module_param(max_lun, ullong, 0444);
module_param(ql2xmaxlun, ullong, S_IRUGO);
module_param_named(default_dev_flags, scsi_default_dev_flags, ullong, 0644);
module_param_named(max_luns, max_scsi_luns, ullong, S_IRUGO|S_IWUSR);
module_param(quirks, ullong, S_IRUGO);
module_param_hw(mem_address, ullong, other, 0400);
STANDARD_PARAM_DEF(ullong, unsigned long long, "%llu", kstrtoull);
__param(ullong, seed, 3141592653589793238ULL, "Random seed");
__param(ullong, seed, 3141592653589793238ULL, "Random seed");