ub960_rxport_write
ub960_rxport_write(priv, chan_id, UB960_RR_SLAVE_ID(reg_idx),
ub960_rxport_write(priv, chan_id, UB960_RR_SLAVE_ALIAS(reg_idx),
ret = ub960_rxport_write(priv, chan_id, UB960_RR_SLAVE_ALIAS(reg_idx),
ret = ub960_rxport_write(priv, nport, UB960_RR_AEQ_BYPASS, v, NULL);
ub960_rxport_write(priv, nport, UB960_RR_AEQ_MIN_MAX,
ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_HI, 0x07, &ret);
ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_LO, 0x7f, &ret);
ub960_rxport_write(priv, nport, UB960_RR_SER_ALIAS_ID,
ub960_rxport_write(priv, nport, UB9702_RR_RX_CTL_2, 0x1b, &ret);
ub960_rxport_write(priv, nport, UB9702_RR_RX_CTL_1, 0x15, &ret);
ub960_rxport_write(priv, nport, UB9702_RR_CHANNEL_MODE, 0x0, &ret);
ub960_rxport_write(priv, nport, UB9702_RR_CHANNEL_MODE, 0x1, &ret);
ub960_rxport_write(priv, nport, UB9702_RR_CHANNEL_MODE, 0x2, &ret);
ub960_rxport_write(priv, nport, UB9702_RR_CHANNEL_MODE, 0x5, &ret);
ub960_rxport_write(priv, it.nport, UB960_RR_SER_ID,
ub960_rxport_write(priv, it.nport, UB960_RR_SER_ALIAS_ID,
ub960_rxport_write(priv, it.nport, UB9702_RR_RX_SM_SEL_2, 0x10,
ret = ub960_rxport_write(priv, it.nport,
ret = ub960_rxport_write(priv, it.nport,
ret = ub960_rxport_write(priv, it.nport,
ub960_rxport_write(priv, it.nport, UB960_RR_PORT_ICR_HI, 0x07,
ub960_rxport_write(priv, it.nport, UB960_RR_PORT_ICR_LO, 0x7f,
ub960_rxport_write(priv, nport, UB960_RR_RAW10_ID,
ub960_rxport_write(priv, nport,
ub960_rxport_write(priv, nport, UB960_RR_CSI_VC_MAP,
ub960_rxport_write(priv, nport,