arch/mips/include/asm/uasm.h

198

int uasm_rel_lo(long val);

arch/mips/kvm/entry.c

328

UASM_i_LW(&p, GPR_T2, uasm_rel_lo((long)&cpu_data[0].asid_mask), GPR_AT);

arch/mips/kvm/entry.c

598

UASM_i_LW(&p, GPR_K0, uasm_rel_lo((long)&ebase), GPR_K0);

arch/mips/kvm/entry.c

707

uasm_i_lw(&p, GPR_K0, uasm_rel_lo((long)&hwrena), GPR_K0);

arch/mips/kvm/entry.c

853

uasm_i_lw(&p, GPR_K0, uasm_rel_lo((long)&hwrena), GPR_K0);

arch/mips/mm/page.c

105

uasm_i_addiu(buf, GPR_T9, GPR_T9, uasm_rel_lo(off));

arch/mips/mm/page.c

98

uasm_i_addiu(buf, GPR_T9, GPR_T9, uasm_rel_lo(off));

arch/mips/mm/tlbex.c

1585

UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);

arch/mips/mm/tlbex.c

1588

UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);

arch/mips/mm/tlbex.c

1866

uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);

arch/mips/mm/tlbex.c

2219

uasm_i_addiu(&p, GPR_K0, GPR_K0, uasm_rel_lo((long)tlb_do_page_fault_0));

arch/mips/mm/tlbex.c

2275

uasm_i_addiu(&p, GPR_K0, GPR_K0, uasm_rel_lo((long)tlb_do_page_fault_1));

arch/mips/mm/tlbex.c

2332

uasm_i_addiu(&p, GPR_K0, GPR_K0, uasm_rel_lo((long)tlb_do_page_fault_1));

arch/mips/mm/tlbex.c

399

uasm_i_lw(&p, GPR_K1, uasm_rel_lo(pgdc), GPR_K1);

arch/mips/mm/tlbex.c

815

uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);

arch/mips/mm/tlbex.c

818

uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);

arch/mips/mm/tlbex.c

859

single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd);

arch/mips/mm/tlbex.c

881

uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));

arch/mips/mm/tlbex.c

883

uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));

arch/mips/mm/tlbex.c

945

uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);

arch/mips/mm/uasm.c

456

UASM_EXPORT_SYMBOL(uasm_rel_lo);

arch/mips/mm/uasm.c

479

if (uasm_rel_lo(addr)) {

arch/mips/mm/uasm.c

482

uasm_rel_lo(addr));

arch/mips/mm/uasm.c

485

uasm_rel_lo(addr));