uart_port_tx_limited
uart_port_tx_limited(port, ch, 256,
uart_port_tx_limited(port, ch, count,
uart_port_tx_limited(port, ch, port->fifosize >> 1,
uart_port_tx_limited(port, ch, port->fifosize,
pending = uart_port_tx_limited(port, ch,
pending = uart_port_tx_limited(port, ch,
uart_port_tx_limited(&up->port, ch, count,
uart_port_tx_limited(port, ch,
uart_port_tx_limited(port, ch, port->fifosize,
uart_port_tx_limited(&up->port, ch, up->port.fifosize / 4,
uart_port_tx_limited(&up->port, ch, up->port.fifosize / 2,
uart_port_tx_limited(&up->port, ch,
uart_port_tx_limited(up, ch, TXX9_SIO_TX_FIFO,
uart_port_tx_limited(&ssp->port, ch, SIFIVE_TX_FIFO_DEPTH,
uart_port_tx_limited(port, ch, THLD_TX_EMPTY,
uart_port_tx_limited(port, ch, asc_hw_txroom(port),