Symbol: tiling_mode
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1003
if (tiling_mode[i] == bw_def_linear) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
107
enum bw_defines *tiling_mode;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1107
if (data->scatter_gather_enable_for_pipe[i] == 1 && tiling_mode[i] != bw_def_linear) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1110
else if (data->scatter_gather_enable_for_pipe[i] == 1 && tiling_mode[i] == bw_def_linear && bw_equ(bw_mod((bw_mul(data->pitch_in_pixels_after_surface_type[i], bw_int_to_fixed(data->bytes_per_pixel[i]))), data->inefficient_linear_pitch_in_bytes), bw_int_to_fixed(0))) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
131
tiling_mode = kzalloc_objs(*tiling_mode, maximum_number_of_surfaces);
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
132
if (!tiling_mode)
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2033
kfree(tiling_mode);
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
274
tiling_mode[0] = bw_def_linear;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
275
tiling_mode[1] = bw_def_linear;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
276
tiling_mode[2] = bw_def_linear;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
277
tiling_mode[3] = bw_def_linear;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
280
tiling_mode[0] = bw_def_landscape;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
281
tiling_mode[1] = bw_def_landscape;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
282
tiling_mode[2] = bw_def_landscape;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
283
tiling_mode[3] = bw_def_landscape;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
339
tiling_mode[i] = bw_def_linear;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
342
tiling_mode[i] = bw_def_tiled;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
386
tiling_mode[maximum_number_of_surfaces - 2] = bw_def_linear;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
387
tiling_mode[maximum_number_of_surfaces - 1] = bw_def_linear;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
594
if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) && (tiling_mode[i] == bw_def_linear || data->stereo_mode[i] != bw_def_mono)) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
693
else if (tiling_mode[i] == bw_def_linear) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
874
if ((dceip->dmif_pipe_en_fbc_chunk_tracker + 3 == i && fbc_enabled == 0 && tiling_mode[i] != bw_def_linear)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10908
calculate_mcache_setting_params->tiling_mode = display_cfg->plane_descriptors[k].surface.tiling;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2328
DML_LOG_VERBOSE("DML::%s: tiling_mode = %u\n", __func__, p->tiling_mode);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2350
blk_bytes = dml_get_tile_block_size_bytes(p->tiling_mode);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2493
l->l_p.tiling_mode = p->tiling_mode;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2536
l->c_p.tiling_mode = p->tiling_mode;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9428
calculate_mcache_setting_params->tiling_mode = display_cfg->plane_descriptors[k].surface.tiling;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h
2065
unsigned int tiling_mode;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h
2134
unsigned int tiling_mode;
drivers/gpu/drm/i915/gem/i915_gem_tiling.c
162
int tiling_mode, unsigned int stride)
drivers/gpu/drm/i915/gem/i915_gem_tiling.c
170
size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride);
drivers/gpu/drm/i915/gem/i915_gem_tiling.c
174
alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride);
drivers/gpu/drm/i915/gem/i915_gem_tiling.c
184
int tiling_mode, unsigned int stride)
drivers/gpu/drm/i915/gem/i915_gem_tiling.c
192
if (tiling_mode == I915_TILING_NONE)
drivers/gpu/drm/i915/gem/i915_gem_tiling.c
201
if (i915_vma_fence_prepare(vma, tiling_mode, stride))
drivers/gpu/drm/i915/gem/i915_gem_tiling.c
367
if (!i915_tiling_ok(obj, args->tiling_mode, args->stride)) {
drivers/gpu/drm/i915/gem/i915_gem_tiling.c
372
if (args->tiling_mode == I915_TILING_NONE) {
drivers/gpu/drm/i915/gem/i915_gem_tiling.c
376
if (args->tiling_mode == I915_TILING_X)
drivers/gpu/drm/i915/gem/i915_gem_tiling.c
395
args->tiling_mode = I915_TILING_NONE;
drivers/gpu/drm/i915/gem/i915_gem_tiling.c
401
err = i915_gem_object_set_tiling(obj, args->tiling_mode, args->stride);
drivers/gpu/drm/i915/gem/i915_gem_tiling.c
405
args->tiling_mode = i915_gem_object_get_tiling(obj);
drivers/gpu/drm/i915/gem/i915_gem_tiling.c
440
args->tiling_mode =
drivers/gpu/drm/i915/gem/i915_gem_tiling.c
448
switch (args->tiling_mode) {
drivers/gpu/drm/i915/gvt/dmabuf.c
218
unsigned int tiling_mode = 0;
drivers/gpu/drm/i915/gvt/dmabuf.c
223
tiling_mode = I915_TILING_NONE;
drivers/gpu/drm/i915/gvt/dmabuf.c
226
tiling_mode = I915_TILING_X;
drivers/gpu/drm/i915/gvt/dmabuf.c
231
tiling_mode = I915_TILING_Y;
drivers/gpu/drm/i915/gvt/dmabuf.c
238
obj->tiling_and_stride = tiling_mode | stride;
include/uapi/drm/i915_drm.h
1758
__u32 tiling_mode;
include/uapi/drm/i915_drm.h
1781
__u32 tiling_mode;
tools/perf/trace/beauty/include/uapi/drm/i915_drm.h
1758
__u32 tiling_mode;
tools/perf/trace/beauty/include/uapi/drm/i915_drm.h
1781
__u32 tiling_mode;