drivers/gpu/drm/tilcdc/tilcdc_crtc.c

104

tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

106

tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

119

tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_PL_INT_ENA);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

135

tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, LCDC_V2_PL_INT_ENA);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

149

tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

167

tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

255

tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

292

tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

321

tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

329

tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

335

tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

378

tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

700

tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_FRAME_DONE);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

907

tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

931

tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

952

tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);

drivers/gpu/drm/tilcdc/tilcdc_regs.h

143

tilcdc_write(dev, reg, (tilcdc_read(dev, reg) & ~mask) | (val & mask));

drivers/gpu/drm/tilcdc/tilcdc_regs.h

148

tilcdc_write(dev, reg, tilcdc_read(dev, reg) | mask);

drivers/gpu/drm/tilcdc/tilcdc_regs.h

153

tilcdc_write(dev, reg, tilcdc_read(dev, reg) & ~mask);

drivers/gpu/drm/tilcdc/tilcdc_regs.h

170

tilcdc_write(dev, tilcdc_irqstatus_reg(dev), mask);