tw32_f
tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
tw32_f(MAC_RX_MODE, RX_MODE_RESET);
tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
tw32_f(WDMAC_MODE, val);
tw32_f(RDMAC_MODE, rdmac_mode);
tw32_f(MAC_TX_MODE, tp->tx_mode);
tw32_f(MAC_RX_MODE, tp->rx_mode);
tw32_f(MAC_RX_MODE, RX_MODE_RESET);
tw32_f(MAC_RX_MODE, tp->rx_mode);
tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
tw32_f(MAC_MODE,
tw32_f(MAC_MODE, tp->mac_mode);
tw32_f(MAC_MI_MODE,
tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
tw32_f(MAC_MI_COM, frame_val);
tw32_f(MAC_MI_MODE, tp->mi_mode);
tw32_f(MAC_MI_MODE,
tw32_f(MAC_MI_COM, frame_val);
tw32_f(MAC_MI_MODE, tp->mi_mode);
tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
tw32_f(MAC_MI_MODE, tp->mi_mode);
tw32_f(GRC_EEPROM_ADDR,
tw32_f(GRC_LOCAL_CTRL,
tw32_f(GRC_RX_CPU_EVENT, val);
tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
tw32_f(MAC_RX_MODE, tp->rx_mode);
tw32_f(MAC_TX_MODE, tp->tx_mode);
tw32_f(MAC_MODE, tp->mac_mode);
tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
tw32_f(cpu_base + CPU_MODE, 0x00000000);
tw32_f(cpu_base + CPU_PC, pc);
tw32_f(cpu_base + CPU_PC, pc);
tw32_f(MAC_MODE, mac_mode);
tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
tw32_f(MAC_STATUS,
tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
tw32_f(TG3_CPMU_EEE_CTRL,
tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
tw32_f(TG3_CPMU_EEE_DBTMR1,
tw32_f(TG3_CPMU_EEE_DBTMR2,
tw32_f(MAC_MI_MODE,
tw32_f(MAC_MI_MODE, tp->mi_mode);
tw32_f(MAC_MODE, tp->mac_mode);
tw32_f(MAC_EVENT, 0);
tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
tw32_f(MAC_STATUS,
tw32_f(MAC_MODE, tp->mac_mode);
tw32_f(MAC_MODE, tp->mac_mode);
tw32_f(MAC_MODE, tp->mac_mode);
tw32_f(MAC_MODE, tp->mac_mode);
tw32_f(MAC_TX_AUTO_NEG, 0);
tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
tw32_f(MAC_MODE, tp->mac_mode);
tw32_f(MAC_SERDES_CFG, val);
tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
tw32_f(MAC_SERDES_CFG, val);
tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
tw32_f(MAC_STATUS,
tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
tw32_f(MAC_MODE, tp->mac_mode);
tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
tw32_f(MAC_TX_AUTO_NEG, 0);
tw32_f(MAC_MODE, tp->mac_mode);
tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
tw32_f(MAC_MODE, (tp->mac_mode |
tw32_f(MAC_MODE, tp->mac_mode);
tw32_f(MAC_MODE, tp->mac_mode);
tw32_f(MAC_MODE, tp->mac_mode);
tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
tw32_f(MAC_MODE, tp->mac_mode);
tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
tw32_f(TG3PCI_MEM_WIN_DATA, val);
tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
tw32_f(MAC_STATUS,
tw32_f(HOSTCC_MODE, tp->coal_now);
tw32_f(MAC_RX_MODE, RX_MODE_RESET);
tw32_f(MAC_RX_MODE, tp->rx_mode);
tw32_f(ofs, val);
tw32_f(MAC_RX_MODE, tp->rx_mode);
tw32_f(MAC_MODE, tp->mac_mode);
tw32_f(MAC_TX_MODE, tp->tx_mode);
tw32_f(MAC_MODE, val);
tw32_f(MAC_RX_MODE, rx_mode);