CTRL1
reg_val = readl(mmio + CTRL1);
writel(reg_val | XMTSP_128 | CACHE_ALIGN, mmio + CTRL1);
writel(CTRL1_DEFAULT, mmio + CTRL1);
.enable_reg = MAX77802_REG_BUCK ## num ## CTRL1, \
.ramp_reg = MAX77802_REG_BUCK ## num ## CTRL1, \
s2mpg10_reg_ldo_ramp_ops, _vrange, CTRL1, GENMASK(6, 0), \
.enable_reg = S2MPU05_REG_B##num##CTRL1, \
regulator_desc_s2mpu05_ldo4(9, CTRL1),
s2mpg10_reg_ldo_ramp_ops, _vrange, CTRL1, GENMASK(6, 0), \
snd_soc_component_update_bits(component, CTRL1, FMT_MASK, priv->ctrl1);