tg3_write_mem
tg3_write_mem(tp, i, 0);
tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
tg3_write_mem(tp, offset + j, test_pattern[i]);
tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
write_op = tg3_write_mem;
tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
tg3_write_mem(tp,
tg3_write_mem(tp,
tg3_write_mem(tp,
tg3_write_mem(tp,
tg3_write_mem(tp,
tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,