tr32
val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
u32 grc_mode = tr32(GRC_MODE);
val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
u32 grc_mode = tr32(GRC_MODE);
val = tr32(TG3_PCIE_TLDLPL_PORT +
val = tr32(TG3_CPMU_PADRNG_CTL);
grc_mode = tr32(GRC_MODE);
val = tr32(TG3_PCIE_TLDLPL_PORT +
val = tr32(TG3_CPMU_LSPD_10MB_CLK);
val = tr32(TG3PCI_PCISTATE);
val = tr32(TG3PCI_PCISTATE);
val = tr32(TG3PCI_MSI_DATA);
val = tr32(TG3PCI_DMA_RW_CTRL) &
val = tr32(TG3PCI_DEV_STATUS_CTRL) & ~MAX_READ_REQ_MASK;
val = tr32(GRC_MISC_CFG);
if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
val |= tr32(MAC_TX_LENGTHS) &
} else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
val = tr32(tgtreg);
val = tr32(tgtreg);
val = tr32(RCVLPC_STATS_ENABLE);
val = tr32(RCVLPC_STATS_ENABLE);
if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
val = tr32(MSGINT_MODE);
} else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
tp->tx_mode |= tr32(MAC_TX_MODE) & val;
val = tr32(MAC_SERDES_CFG);
tmp = tr32(SERDES_RX_CTRL);
clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
do { u32 __val = tr32(REG); \
val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
u32 val = tr32(HOSTCC_FLOW_ATTN);
tr32(HOSTCC_MODE);
if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
mac_stat = tr32(MAC_STATUS);
u32 mac_stat = tr32(MAC_STATUS);
u32 cpmu = tr32(TG3_CPMU_STATUS);
val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
frame_val = tr32(MAC_MI_COM);
frame_val = tr32(MAC_MI_COM);
u32 msi_mode = tr32(MSGINT_MODE);
u32 val = tr32(PCIE_TRANSACTION_CFG);
frame_val = tr32(MAC_MI_COM);
frame_val = tr32(MAC_MI_COM);
cpmu_val = tr32(TG3_CPMU_CTRL);
save_val = tr32(offset);
val = tr32(offset);
val = tr32(offset);
if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
val = tr32(MAC_PHYCFG1);
nvcfg1 = tr32(NVRAM_CFG1);
nvcfg1 = tr32(NVRAM_CFG1);
nvcfg1 = tr32(NVRAM_CFG1);
val = tr32(MAC_PHYCFG1);
nvcfg1 = tr32(NVRAM_CFG1);
nvcfg1 = tr32(NVRAM_CFG1);
tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
val = tr32(MAC_EXT_RGMII_MODE);
nvcfg1 = tr32(NVRAM_CFG1);
nvcfg1 = tr32(NVRAM_CFG1);
nvcfg1 = tr32(NVRAM_CFG1);
nv_status = tr32(NVRAM_AUTOSENSE_STATUS);
tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
val = tr32(VCPU_CFGSHDW);
val = tr32(OTP_STATUS);
thalf_otp = tr32(OTP_READ_DATA);
bhalf_otp = tr32(OTP_READ_DATA);
val = tr32(GRC_RX_CPU_EVENT);
u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
val = tr32(MEMARB_MODE);
val = tr32(TG3_CPMU_STATUS);
tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
val = tr32(GRC_MODE);
grc_misc_cfg = tr32(GRC_MISC_CFG);
tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
hi = tr32(MAC_ADDR_0_HIGH);
lo = tr32(MAC_ADDR_0_LOW);
val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
val = tr32(TG3_CPMU_EEE_MODE);
dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
val = tr32(TG3_CPMU_EEE_MODE);
val = tr32(TG3_CPMU_EEE_MODE);
val = tr32(GRC_MISC_CFG);
cpmuctrl = tr32(TG3_CPMU_CTRL);
val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
status = tr32(TG3_CPMU_DRV_STATUS);
u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
u32 serdes_cfg = tr32(MAC_SERDES_CFG);
val = tr32(GRC_MISC_CFG);
val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
if (tr32(NVRAM_SWARB) & SWARB_GNT1)
u32 nvaccess = tr32(NVRAM_ACCESS);
u32 nvaccess = tr32(NVRAM_ACCESS);
tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
tmp = tr32(GRC_EEPROM_ADDR);
tmp = tr32(GRC_EEPROM_DATA);
if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
*val = tr32(NVRAM_RDDATA);
val = tr32(GRC_EEPROM_ADDR);
val = tr32(GRC_EEPROM_ADDR);
grc_mode = tr32(GRC_MODE);
grc_mode = tr32(GRC_MODE);
if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
u32 val = tr32(GRC_VCPU_EXT_CTRL);
tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
if (tr32(cpu_base + CPU_PC) == pc)
tr32(RX_CPU_BASE + CPU_PC),
if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
__func__, tr32(cpu_base + CPU_PC),
misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
val = tr32(GRC_VCPU_EXT_CTRL);
u32 val = tr32(0x7d00);
tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
u32 led_ctrl = tr32(MAC_LED_CTRL);
if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
u32 mac_status = tr32(MAC_STATUS);
if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
sg_dig_ctrl = tr32(SG_DIG_CTRL);
sg_dig_status = tr32(SG_DIG_STATUS);
mac_status = tr32(MAC_STATUS);
mac_status = tr32(MAC_STATUS);
if ((tr32(MAC_STATUS) &
mac_status = tr32(MAC_STATUS);
mac_status = tr32(MAC_STATUS);
mac_status = tr32(MAC_STATUS);
if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
mac_status = tr32(MAC_STATUS);
if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
val |= tr32(MAC_TX_LENGTHS) &
val = tr32(PCIE_PWR_MGMT_THRESH);
stamp = tr32(TG3_EAV_REF_CLCK_LSB);
stamp |= (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
*hwclock = tr32(TG3_TX_TSTAMP_LSB);
*hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
*dst++ = tr32(off + i);
regs[i / sizeof(u32)] = tr32(i);
*val = tr32(TG3PCI_MEM_WIN_DATA);
tstamp = tr32(TG3_RX_TSTAMP_LSB);
tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
val = tr32(HOSTCC_FLOW_ATTN);
if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
!(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
val = tr32(ofs);
val = tr32(ofs);
if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
"MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
val = tr32(MSGINT_MODE);
val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
val = tr32(TG3_CPMU_CLCK_ORIDE);
val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
tr32(TG3_PCIE_PHY_TSTCTL) ==
tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
val = tr32(MEMARB_MODE);
val = tr32(0xc4);
val = tr32(0x7c00);
val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
addr0_high = tr32(MAC_ADDR_0_HIGH);
addr0_low = tr32(MAC_ADDR_0_LOW);
addr1_high = tr32(MAC_ADDR_1_HIGH);
addr1_low = tr32(MAC_ADDR_1_LOW);
val = tr32(TG3_CPMU_CTRL);
val = tr32(TG3_CPMU_LSPD_10MB_CLK);
val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
val = tr32(TG3_CPMU_HST_ACC);