tegra_dsi_writel
tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
tegra_dsi_writel(dsi, value, DSI_WR_DATA);
tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
tegra_dsi_writel(dsi, value, DSI_CONTROL);
tegra_dsi_writel(dsi, value, DSI_WR_DATA);
tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
tegra_dsi_writel(dsi, value, DSI_CONTROL);
tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
tegra_dsi_writel(dsi, value, DSI_CONTROL);
tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
tegra_dsi_writel(dsi, value, DSI_CONTROL);
tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
tegra_dsi_writel(dsi, 0, DSI_TRIGGER);