Symbol: tegra_dc_writel
drivers/gpu/drm/tegra/dc.c
1050
tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
drivers/gpu/drm/tegra/dc.c
1054
tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
drivers/gpu/drm/tegra/dc.c
1060
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
drivers/gpu/drm/tegra/dc.c
1074
tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
drivers/gpu/drm/tegra/dc.c
1086
tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR);
drivers/gpu/drm/tegra/dc.c
1090
tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR);
drivers/gpu/drm/tegra/dc.c
1098
tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
drivers/gpu/drm/tegra/dc.c
1125
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
drivers/gpu/drm/tegra/dc.c
1184
tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/dc.c
1188
tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/dc.c
152
tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
drivers/gpu/drm/tegra/dc.c
154
tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
drivers/gpu/drm/tegra/dc.c
1786
tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
drivers/gpu/drm/tegra/dc.c
1795
tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
drivers/gpu/drm/tegra/dc.c
1889
tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
drivers/gpu/drm/tegra/dc.c
1901
tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
drivers/gpu/drm/tegra/dc.c
191
tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
drivers/gpu/drm/tegra/dc.c
1926
tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
drivers/gpu/drm/tegra/dc.c
1929
tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
drivers/gpu/drm/tegra/dc.c
1934
tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
drivers/gpu/drm/tegra/dc.c
1938
tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
drivers/gpu/drm/tegra/dc.c
1942
tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
drivers/gpu/drm/tegra/dc.c
1945
tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
drivers/gpu/drm/tegra/dc.c
2069
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
drivers/gpu/drm/tegra/dc.c
223
tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/dc.c
2232
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
drivers/gpu/drm/tegra/dc.c
224
tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/dc.c
2287
tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
drivers/gpu/drm/tegra/dc.c
2290
tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
drivers/gpu/drm/tegra/dc.c
2296
tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
drivers/gpu/drm/tegra/dc.c
2303
tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
drivers/gpu/drm/tegra/dc.c
2307
tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
drivers/gpu/drm/tegra/dc.c
2310
tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
drivers/gpu/drm/tegra/dc.c
2312
tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
drivers/gpu/drm/tegra/dc.c
2316
tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
drivers/gpu/drm/tegra/dc.c
2320
tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
drivers/gpu/drm/tegra/dc.c
2325
tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
drivers/gpu/drm/tegra/dc.c
2329
tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
drivers/gpu/drm/tegra/dc.c
2333
tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
drivers/gpu/drm/tegra/dc.c
2337
tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
drivers/gpu/drm/tegra/dc.c
2341
tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
drivers/gpu/drm/tegra/dc.c
2343
tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
drivers/gpu/drm/tegra/dc.c
2348
tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
drivers/gpu/drm/tegra/dc.c
2358
tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
drivers/gpu/drm/tegra/dc.c
2364
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
drivers/gpu/drm/tegra/dc.c
2370
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
drivers/gpu/drm/tegra/dc.c
2376
tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
drivers/gpu/drm/tegra/dc.c
2382
tegra_dc_writel(dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
drivers/gpu/drm/tegra/dc.c
2421
tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/dc.c
2425
tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/dc.c
2640
tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
drivers/gpu/drm/tegra/dsi.c
865
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
drivers/gpu/drm/tegra/dsi.c
943
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
drivers/gpu/drm/tegra/hdmi.c
1186
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
drivers/gpu/drm/tegra/hdmi.c
1264
tegra_dc_writel(dc, VSYNC_H_POSITION(1),
drivers/gpu/drm/tegra/hdmi.c
1266
tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
drivers/gpu/drm/tegra/hdmi.c
1272
tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
drivers/gpu/drm/tegra/hdmi.c
1276
tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
drivers/gpu/drm/tegra/hdmi.c
1279
tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
drivers/gpu/drm/tegra/hdmi.c
1423
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
drivers/gpu/drm/tegra/hub.c
111
tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
drivers/gpu/drm/tegra/hub.c
202
tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/hub.c
222
tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/hub.c
294
tegra_dc_writel(dc, value, offset);
drivers/gpu/drm/tegra/hub.c
913
tegra_dc_writel(dc, value, DC_CMD_IHUB_COMMON_MISC_CTL);
drivers/gpu/drm/tegra/hub.c
917
tegra_dc_writel(dc, value, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER);
drivers/gpu/drm/tegra/hub.c
919
tegra_dc_writel(dc, COMMON_UPDATE, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/hub.c
921
tegra_dc_writel(dc, COMMON_ACTREQ, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/rgb.c
110
tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
drivers/gpu/drm/tegra/rgb.c
125
tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
drivers/gpu/drm/tegra/rgb.c
130
tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
drivers/gpu/drm/tegra/rgb.c
88
tegra_dc_writel(dc, table[i].value, table[i].offset);
drivers/gpu/drm/tegra/sor.c
2235
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
drivers/gpu/drm/tegra/sor.c
2460
tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
drivers/gpu/drm/tegra/sor.c
2463
tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
drivers/gpu/drm/tegra/sor.c
2467
tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
drivers/gpu/drm/tegra/sor.c
2557
tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
drivers/gpu/drm/tegra/sor.c
2564
tegra_dc_writel(dc, lower_32_bits(dc->cmu_output_lut_phys),
drivers/gpu/drm/tegra/sor.c
2566
tegra_dc_writel(dc, upper_32_bits(dc->cmu_output_lut_phys),
drivers/gpu/drm/tegra/sor.c
2569
tegra_dc_writel(dc, OUTPUT_LUT_MODE_INTERPOLATE | OUTPUT_LUT_SIZE_SIZE_1025,
drivers/gpu/drm/tegra/sor.c
2598
tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
drivers/gpu/drm/tegra/sor.c
2643
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
drivers/gpu/drm/tegra/sor.c
2649
tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
drivers/gpu/drm/tegra/sor.c
2699
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
drivers/gpu/drm/tegra/sor.c
2940
tegra_dc_writel(dc, lower_32_bits(dc->cmu_output_lut_phys),
drivers/gpu/drm/tegra/sor.c
2942
tegra_dc_writel(dc, upper_32_bits(dc->cmu_output_lut_phys),
drivers/gpu/drm/tegra/sor.c
2945
tegra_dc_writel(dc, OUTPUT_LUT_MODE_INTERPOLATE | OUTPUT_LUT_SIZE_SIZE_1025,
drivers/gpu/drm/tegra/sor.c
2949
tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
drivers/gpu/drm/tegra/sor.c
2954
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);