tegra_clock_set_pd_state
ret = tegra_clock_set_pd_state(clk_dev, rate);
err = tegra_clock_set_pd_state(clk_dev, cnd->new_rate);
err = tegra_clock_set_pd_state(clk_dev, cnd->old_rate);
err = tegra_clock_set_pd_state(clk_dev, cnd->new_rate);