tegra_clk_cile
MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, tegra_clk_cile),
[tegra_clk_cile] = { .dt_id = TEGRA114_CLK_CILE, .present = true },
[tegra_clk_cile] = { .dt_id = TEGRA124_CLK_CILE, .present = true },
[tegra_clk_cile] = { .dt_id = TEGRA210_CLK_CILE, .present = true },