CT2_PCIE_MISC_REG
r32 = readl(rb + CT2_PCIE_MISC_REG);
rb + CT2_PCIE_MISC_REG);
r32 = readl((rb + CT2_PCIE_MISC_REG));
writel(r32 | __ETH_CLK_ENABLE_PORT1, (rb + CT2_PCIE_MISC_REG));