drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

161

CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

162

CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

163

CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

164

CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

168

CS_SF(OTG0_PIXEL_RATE_CNTL, PIPE0_DTO_SRC_SEL, mask_sh),

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

172

CS_SF(OTG0_PIXEL_RATE_CNTL, PIPE0_DTO_SRC_SEL, mask_sh)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

190

CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

191

CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

192

CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

193

CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

49

CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

50

CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

51

CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

52

CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

55

CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

56

CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)