to_clk
to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
to_clk(imx_clk_hw_fixed(name, rate))
to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))
to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
to_clk(imx_clk_hw_gate(name, parent, reg, shift))
to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
to_clk(__imx_clk_hw_gate2(name, parent, reg, shift, cgr_val, 0, NULL))
to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
to_clk(imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags))
to_clk(imx_clk_hw_pllv1(type, name, parent, base))
to_clk(imx_clk_hw_pllv2(name, parent, base))