tn40_write_reg
tn40_write_reg(priv, 0x103c, 0x81644); /*ETHSD.L0_TX_DCNT */
tn40_write_reg(priv, 0x1040, 0x81644); /*ETHSD.L1_TX_DCNT */
tn40_write_reg(priv, 0x1044, 0x81644); /*ETHSD.L2_TX_DCNT */
tn40_write_reg(priv, 0x1048, 0x81644); /*ETHSD.L3_TX_DCNT */
tn40_write_reg(priv, 0x1014, 0x043); /*ETHSD.INIT_STAT */
tn40_write_reg(priv, 0x1014, 0x3);
tn40_write_reg(priv, 0x6350, 0x0); /*MAC.PCS_IF_MODE */
tn40_write_reg(priv, TN40_REG_CTRLST, 0xC13); /*0x93//0x13 */
tn40_write_reg(priv, 0x111c, 0x7ff); /*MAC.MAC_RST_CNT */
tn40_write_reg(priv, 0x111c, 0x0); /*MAC.MAC_RST_CNT */
tn40_write_reg(priv, 0x1010, 0x613); /*ETHSD.REFCLK_CONF */
tn40_write_reg(priv, 0x104c, 0x4d); /*ETHSD.L0_RX_PCNT */
tn40_write_reg(priv, 0x1050, 0x0); /*ETHSD.L1_RX_PCNT */
tn40_write_reg(priv, 0x1054, 0x0); /*ETHSD.L2_RX_PCNT */
tn40_write_reg(priv, 0x1058, 0x0); /*ETHSD.L3_RX_PCNT */
tn40_write_reg(priv, 0x102c, 0x35); /*ETHSD.L0_TX_PCNT */
tn40_write_reg(priv, 0x1030, 0x0); /*ETHSD.L1_TX_PCNT */
tn40_write_reg(priv, 0x1034, 0x0); /*ETHSD.L2_TX_PCNT */
tn40_write_reg(priv, 0x1038, 0x0); /*ETHSD.L3_TX_PCNT */
tn40_write_reg(priv, 0x6300, 0x01140); /*MAC.PCS_CTRL */
tn40_write_reg(priv, 0x1014, 0x043); /*ETHSD.INIT_STAT */
tn40_write_reg(priv, 0x1014, 0x3);
tn40_write_reg(priv, 0x6350, 0x2b); /*MAC.PCS_IF_MODE 1g */
tn40_write_reg(priv, 0x6310, 0x9801); /*MAC.PCS_DEV_AB */
tn40_write_reg(priv, 0x6314, 0x1); /*MAC.PCS_PART_AB */
tn40_write_reg(priv, 0x6348, 0xc8); /*MAC.PCS_LINK_LO */
tn40_write_reg(priv, 0x634c, 0xc8); /*MAC.PCS_LINK_HI */
tn40_write_reg(priv, TN40_REG_CTRLST, 0xC13); /*0x93//0x13 */
tn40_write_reg(priv, 0x111c, 0x7ff); /*MAC.MAC_RST_CNT */
tn40_write_reg(priv, 0x111c, 0x0); /*MAC.MAC_RST_CNT */
tn40_write_reg(priv, 0x6300, 0x1140); /*MAC.PCS_CTRL */
tn40_write_reg(priv, 0x104c, 0x0); /*ETHSD.L0_RX_PCNT */
tn40_write_reg(priv, 0x1050, 0x0); /*ETHSD.L1_RX_PCNT */
tn40_write_reg(priv, 0x1054, 0x0); /*ETHSD.L2_RX_PCNT */
tn40_write_reg(priv, 0x1058, 0x0); /*ETHSD.L3_RX_PCNT */
tn40_write_reg(priv, 0x102c, 0x0); /*ETHSD.L0_TX_PCNT */
tn40_write_reg(priv, 0x1030, 0x0); /*ETHSD.L1_TX_PCNT */
tn40_write_reg(priv, 0x1034, 0x0); /*ETHSD.L2_TX_PCNT */
tn40_write_reg(priv, 0x1038, 0x0); /*ETHSD.L3_TX_PCNT */
tn40_write_reg(priv, TN40_REG_CTRLST, 0x800);
tn40_write_reg(priv, 0x111c, 0x7ff); /*MAC.MAC_RST_CNT */
tn40_write_reg(priv, 0x111c, 0x0); /*MAC.MAC_RST_CNT */
tn40_write_reg(priv, TN40_REG_INIT_SEMAPHORE, 1);
tn40_write_reg(priv, TN40_REG_UNC_MAC2_A, val);
tn40_write_reg(priv, TN40_REG_UNC_MAC1_A, val);
tn40_write_reg(priv, TN40_REG_UNC_MAC0_A, val);
tn40_write_reg(priv, TN40_REG_MAC_ADDR_0,
tn40_write_reg(priv, TN40_REG_MAC_ADDR_1,
tn40_write_reg(priv, TN40_REG_FRM_LENGTH, 0X3FE0);
tn40_write_reg(priv, TN40_REG_GMAC_RXF_A, 0X10fd);
tn40_write_reg(priv, 0x103c, 0x81644); /*ETHSD.L0_TX_DCNT */
tn40_write_reg(priv, 0x1040, 0x81644); /*ETHSD.L1_TX_DCNT */
tn40_write_reg(priv, 0x1044, 0x81644); /*ETHSD.L2_TX_DCNT */
tn40_write_reg(priv, 0x1048, 0x81644); /*ETHSD.L3_TX_DCNT */
tn40_write_reg(priv, TN40_REG_RX_FIFO_SECTION, 0x10);
tn40_write_reg(priv, TN40_REG_TX_FIFO_SECTION, 0xE00010);
tn40_write_reg(priv, TN40_REG_RX_FULLNESS, 0);
tn40_write_reg(priv, TN40_REG_TX_FULLNESS, 0);
tn40_write_reg(priv, TN40_REG_VGLB, 0);
tn40_write_reg(priv, TN40_REG_MAX_FRAME_A,
tn40_write_reg(priv, TN40_REG_RDINTCM0, priv->rdintcm);
tn40_write_reg(priv, TN40_REG_RDINTCM2, 0);
tn40_write_reg(priv, TN40_REG_TDINTCM0, priv->tdintcm);
tn40_write_reg(priv, 0x12E0, 0x28);
tn40_write_reg(priv, TN40_REG_PAUSE_QUANT, 0xFFFF);
tn40_write_reg(priv, 0x6064, 0xF);
tn40_write_reg(priv, TN40_REG_GMAC_RXF_A,
tn40_write_reg(priv, TN40_REG_CLKPLL, (val | TN40_CLKPLL_SFTRST) + 0x8);
tn40_write_reg(priv, TN40_REG_CLKPLL, val & ~TN40_CLKPLL_SFTRST);
tn40_write_reg(priv, TN40_REG_GMAC_RXF_A, 0);
tn40_write_reg(priv, TN40_REG_DIS_PORT, 1);
tn40_write_reg(priv, TN40_REG_DIS_QU, 1);
tn40_write_reg(priv, TN40_REG_RDINTCM0, 0);
tn40_write_reg(priv, TN40_REG_TDINTCM0, 0);
tn40_write_reg(priv, TN40_REG_IMR, 0);
tn40_write_reg(priv, TN40_REG_RST_QU, 1);
tn40_write_reg(priv, TN40_REG_RST_PORT, 1);
tn40_write_reg(priv, i, 0);
tn40_write_reg(priv, TN40_REG_DIS_PORT, 0);
tn40_write_reg(priv, TN40_REG_DIS_QU, 0);
tn40_write_reg(priv, TN40_REG_RST_QU, 0);
tn40_write_reg(priv, TN40_REG_RST_PORT, 0);
tn40_write_reg(priv, reg, val);
tn40_write_reg(priv,
tn40_write_reg(priv,
tn40_write_reg(priv,
tn40_write_reg(priv,
tn40_write_reg(priv, reg, val);
tn40_write_reg(priv, TN40_REG_GMAC_RXF_A, rxf_val);
tn40_write_reg(priv, 0x51E0, 0x30010006); /* GPIO_OE_ WR CMD */
tn40_write_reg(priv, 0x51F0, 0x0); /* GPIO_OE_ DATA */
tn40_write_reg(priv, TN40_REG_MDIO_CMD_STAT, 0x3ec8);
tn40_write_reg(priv, TN40_REG_IMR, priv->isr_mask);
tn40_write_reg(priv, f->m.reg_wptr,
tn40_write_reg(priv, TN40_REG_IMR, 0);
tn40_write_reg(priv, f->m.reg_wptr, f->m.wptr & TN40_TXF_WPTR_WR_PTR);
tn40_write_reg(priv, f->m.reg_rptr, f->m.rptr & TN40_TXF_WPTR_WR_PTR);
tn40_write_reg(priv, reg_cfg0, cfg_base);
tn40_write_reg(priv, reg_cfg1, upper_32_bits(f->da));
tn40_write_reg(priv, f->m.reg_wptr,
tn40_write_reg(priv, f->m.reg_wptr,
tn40_write_reg(priv, f->m.reg_rptr, f->m.rptr & TN40_TXF_WPTR_WR_PTR);
tn40_write_reg(priv, priv->txd_fifo0.m.reg_wptr,
tn40_write_reg(priv, f->m.reg_wptr, f->m.wptr & TN40_TXF_WPTR_WR_PTR);
tn40_write_reg(priv, 0x1010, 0x217); /*ETHSD.REFCLK_CONF */
tn40_write_reg(priv, 0x104c, 0x4c); /*ETHSD.L0_RX_PCNT */
tn40_write_reg(priv, 0x1050, 0x4c); /*ETHSD.L1_RX_PCNT */
tn40_write_reg(priv, 0x1054, 0x4c); /*ETHSD.L2_RX_PCNT */
tn40_write_reg(priv, 0x1058, 0x4c); /*ETHSD.L3_RX_PCNT */
tn40_write_reg(priv, 0x102c, 0x434); /*ETHSD.L0_TX_PCNT */
tn40_write_reg(priv, 0x1030, 0x434); /*ETHSD.L1_TX_PCNT */
tn40_write_reg(priv, 0x1034, 0x434); /*ETHSD.L2_TX_PCNT */
tn40_write_reg(priv, 0x1038, 0x434); /*ETHSD.L3_TX_PCNT */
tn40_write_reg(priv, 0x6300, 0x0400); /*MAC.PCS_CTRL */
tn40_write_reg(priv, 0x1018, 0x00); /*Mike2 */
tn40_write_reg(priv, 0x1018, 0x04); /*Mike2 */
tn40_write_reg(priv, 0x1018, 0x06); /*Mike2 */