tn40_read_reg
val = tn40_read_reg(priv, 0x1014);
val = tn40_read_reg(priv, 0x1014);
val = tn40_read_reg(priv, 0x1014); /*ETHSD.INIT_STAT */
val = tn40_read_reg(priv, 0x1014);
u32 link = tn40_read_reg(priv,
isr = tn40_read_reg(priv, TN40_REG_ISR_MSK0);
tn40_read_reg(priv, TN40_REG_TXF_WPTR_0);
tn40_read_reg(priv, TN40_REG_RXD_WPTR_0);
master = tn40_read_reg(priv, TN40_REG_INIT_SEMAPHORE);
if (!tn40_read_reg(priv, TN40_REG_INIT_STATUS) && master) {
ret = read_poll_timeout(tn40_read_reg, val, val, 2000, 400000, false,
tn40_read_reg(priv, TN40_REG_VPC),
tn40_read_reg(priv, TN40_REG_VIC),
tn40_read_reg(priv, TN40_REG_INIT_STATUS));
tn40_read_reg(priv, TN40_REG_UNC_MAC0_A),
tn40_read_reg(priv, TN40_REG_UNC_MAC1_A),
tn40_read_reg(priv, TN40_REG_UNC_MAC2_A));
tn40_read_reg(priv, TN40_REG_UNC_MAC0_A),
tn40_read_reg(priv, TN40_REG_UNC_MAC1_A),
tn40_read_reg(priv, TN40_REG_UNC_MAC2_A));
val = tn40_read_reg(priv, TN40_REG_CLKPLL);
val = tn40_read_reg(priv, TN40_REG_CLKPLL);
val = read_poll_timeout(tn40_read_reg, val,
tn40_read_reg(priv, TN40_REG_RXD_CFG0_0);
ret = read_poll_timeout(tn40_read_reg, val, val & 1, 10000, 500000,
tn40_read_reg(priv, TN40_REG_ISR);
val = tn40_read_reg(priv, reg);
val = tn40_read_reg(priv, reg);
val = (u64)tn40_read_reg(priv, TN40_REG_UNC_MAC0_A);
val |= (u64)tn40_read_reg(priv, TN40_REG_UNC_MAC1_A) << 16;
val |= (u64)tn40_read_reg(priv, TN40_REG_UNC_MAC2_A) << 32;
((tn40_read_reg(priv, TN40_FPGA_VER) & 0xFFF) != 308);
f->m.reg_rptr, tn40_read_reg(priv, f->m.reg_rptr));
f->m.reg_wptr, tn40_read_reg(priv, f->m.reg_wptr));
f->m.wptr = tn40_read_reg(priv, f->m.reg_wptr) & TN40_TXF_WPTR_WR_PTR;
f->m.rptr = tn40_read_reg(priv, f->m.reg_rptr) & TN40_TXF_WPTR_WR_PTR;
f->m.wptr = tn40_read_reg(priv, f->m.reg_wptr) & TN40_TXF_WPTR_MASK;