CSR12
lance->RAP = CSR12; /* Physical Address Register, PADR[15:0] */
iowrite32(0x1301, ioaddr + CSR12); /* Trigger NWAY. */
int csr12 = ioread32(ioaddr + CSR12);
ioread32(ioaddr + CSR12));
iowrite32(0x0301, ioaddr + CSR12);
int csr12 = ioread32(ioaddr + CSR12);
iowrite32(0x0301, ioaddr + CSR12);
int csr12 = ioread32(tp->base_addr + CSR12) & 0xff;
iowrite32(csr12 | 0x02, tp->base_addr + CSR12);
iowrite32(csr12 & ~0x02, tp->base_addr + CSR12);
iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
iowrite32(p[1], ioaddr + CSR12);
iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
iowrite32(reset_sequence[i], ioaddr + CSR12);
ioread32(ioaddr + CSR12);
iowrite32(init_sequence[i], ioaddr + CSR12);
ioread32(ioaddr + CSR12); /* flush posted writes */
ioread32(ioaddr + CSR12) & 0xff);
iowrite32(0x32, ioaddr + CSR12);
iowrite32(0x33, ioaddr + CSR12);
iowrite32(0x32, ioaddr + CSR12);
ioread32(ioaddr + CSR12));
int csr12 = ioread32(ioaddr + CSR12);
iowrite32(0x33, ioaddr + CSR12);
iowrite32(0x32, ioaddr + CSR12);
iowrite32(0x32 | (dev->if_port & 1), ioaddr + CSR12);
iowrite32(0x30, ioaddr + CSR12);
csr12 = (ioread32(ioaddr + CSR12) & 0xffff8fff);
iowrite32(csr12, ioaddr + CSR12);
int csr12 = ioread32(ioaddr + CSR12);
ioread32(ioaddr + CSR12));
ioread32(ioaddr + CSR12));
ioread32(ioaddr + CSR12));
u32 csr12 = ioread32(ioaddr + CSR12);
iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
iowrite32(0x30, ioaddr + CSR12);
iowrite32(0x00001000, ioaddr + CSR12);
iowrite32(0x32, ioaddr + CSR12);
ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
(int)ioread32(ioaddr + CSR12));
ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
int csr12 = ioread32 (ioaddr + CSR12);
val = xr8(CSR12);
reg = rt2x00mmio_register_read(rt2x00dev, CSR12);
rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
reg = rt2x00mmio_register_read(rt2x00dev, CSR12);
rt2x00mmio_register_write(rt2x00dev, CSR12, reg);