timer_val
int read_current_timer(unsigned long *timer_val)
*timer_val = delay_timer->read_current_timer();
static inline int read_current_timer(unsigned long *timer_val)
*timer_val = __vmgettime();
static inline int read_current_timer(unsigned long *timer_val)
*timer_val = get_cycles();
int read_current_timer(unsigned long *timer_val)
*timer_val = get_tick();
int read_current_timer(unsigned long *timer_val)
*timer_val = rdtsc();
mod_timer(&lp->timer, jiffies + lp->timer_val);
lp->timer_val = ISS_NET_TIMER_VALUE;
mod_timer(&lp->timer, jiffies + lp->timer_val);
unsigned int timer_val;
u32 timer_val = ADF_SSM_WDT_DEFAULT_VALUE;
ADF_CSR_WR(pmisc_addr, ADF_SSMWDT(i), timer_val);
u64 timer_val = ADF_SSM_WDT_DEFAULT_VALUE;
ADF_CSR_WR64_LO_HI(pmisc_addr, ADF_SSMWDTL_OFFSET, ADF_SSMWDTH_OFFSET, timer_val);
return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
u16 timer_val[SGE_NTIMERS];
for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
delta = time - s->timer_val[i];
s->timer_val[0] = core_ticks_to_us(adap,
s->timer_val[1] = core_ticks_to_us(adap,
s->timer_val[2] = core_ticks_to_us(adap,
s->timer_val[3] = core_ticks_to_us(adap,
s->timer_val[4] = core_ticks_to_us(adap,
s->timer_val[5] = core_ticks_to_us(adap,
u16 timer_val[SGE_NTIMERS]; /* interrupt holdoff timer array */
for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
int delta = us - s->timer_val[i];
? adapter->sge.timer_val[timer_idx]
s->timer_val[0] = core_ticks_to_us(adapter,
s->timer_val[1] = core_ticks_to_us(adapter,
s->timer_val[2] = core_ticks_to_us(adapter,
s->timer_val[3] = core_ticks_to_us(adapter,
s->timer_val[4] = core_ticks_to_us(adapter,
s->timer_val[5] = core_ticks_to_us(adapter,
unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20;
tp->tx_lpi_timer = timer_val;
r8168_mac_ocp_write(tp, 0xe048, timer_val);
tp->tx_lpi_timer = timer_val;
RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val);
u32 timer_val = dev->mt76.beacon_int << 4;
timer_val -= 1;
MT_BEACON_TIME_CFG_INTVAL, timer_val);
writel(old->timer_val, priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
old->timer_val = readl(priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
u32 timer_val;
for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
delta = time - s->timer_val[i];
sge->timer_val[0] = (uint16_t)csio_core_ticks_to_us(hw,
sge->timer_val[1] = (uint16_t)csio_core_ticks_to_us(hw,
sge->timer_val[2] = (uint16_t)csio_core_ticks_to_us(hw,
sge->timer_val[3] = (uint16_t)csio_core_ticks_to_us(hw,
sge->timer_val[4] = (uint16_t)csio_core_ticks_to_us(hw,
sge->timer_val[5] = (uint16_t)csio_core_ticks_to_us(hw,
sge->timer_val[0] = CSIO_SGE_TIMER_VAL_0;
sge->timer_val[1] = CSIO_SGE_TIMER_VAL_1;
sge->timer_val[2] = CSIO_SGE_TIMER_VAL_2;
sge->timer_val[3] = CSIO_SGE_TIMER_VAL_3;
sge->timer_val[4] = CSIO_SGE_TIMER_VAL_4;
sge->timer_val[5] = CSIO_SGE_TIMER_VAL_5;
TIMERVALUE0_V(csio_us_to_core_ticks(hw, sge->timer_val[0])) |
TIMERVALUE1_V(csio_us_to_core_ticks(hw, sge->timer_val[1])),
TIMERVALUE2_V(csio_us_to_core_ticks(hw, sge->timer_val[2])) |
TIMERVALUE3_V(csio_us_to_core_ticks(hw, sge->timer_val[3])),
TIMERVALUE4_V(csio_us_to_core_ticks(hw, sge->timer_val[4])) |
TIMERVALUE5_V(csio_us_to_core_ticks(hw, sge->timer_val[5])),
uint16_t timer_val[CSIO_SGE_NTIMERS];
u32 timer_val;
timer_val = ufs_renesas_read(hba, 0xd4) & 0x0000ffff;
return timer_val;
static void ufs_renesas_init_enable_timer(struct ufs_hba *hba, u32 timer_val)
ufs_renesas_write(hba, 0xd4, timer_val);
u32 timer_val;
timer_val = ufs_renesas_init_disable_timer(hba);
ufs_renesas_init_enable_timer(hba, timer_val);
u32 timer_val;
timer_val = ufs_renesas_init_disable_timer(hba);
ufs_renesas_init_enable_timer(hba, timer_val);
u8 timer_val; /* content for the wd_time register */
wd->timer_val = DIV_ROUND_UP(timeout, 60);
timeout = wd->timer_val * 60;
wd->timer_val = timeout;
wd->timer_val);
int read_current_timer(unsigned long *timer_val);
__type(value, struct timer_val);
__type(value, struct timer_val);