timer_base
void orion_time_set_base(void __iomem *timer_base);
u = readl(timer_base + TIMER_CTRL_OFF);
writel(u, timer_base + TIMER_CTRL_OFF);
u = readl(timer_base + TIMER_CTRL_OFF);
writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
u = readl(timer_base + TIMER_CTRL_OFF);
writel(u | TIMER1_EN | TIMER1_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
timer_base = _timer_base;
return ~readl(timer_base + TIMER0_VAL_OFF);
writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
u = readl(timer_base + TIMER_CTRL_OFF);
writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, "orion_clocksource",
static void __iomem *timer_base;
return ~readl(timer_base + TIMER0_VAL_OFF);
writel(delta, timer_base + TIMER1_VAL_OFF);
kona_timer_get_counter(void __iomem *timer_base, uint32_t *msw, uint32_t *lsw)
*msw = readl(timer_base + KONA_GPTIMER_STCHI_OFFSET);
*lsw = readl(timer_base + KONA_GPTIMER_STCLO_OFFSET);
if (*msw == readl(timer_base + KONA_GPTIMER_STCHI_OFFSET))
timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF);
writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF);
return ~readl(timer_base + TIMER0_VAL_OFF);
timer_base = of_iomap(np, 0);
if (!timer_base) {
atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set);
writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
atomic_io_modify(timer_base + TIMER_CTRL_OFF,
res = clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
static void __iomem *timer_base, *local_base;
return ~readl(timer_base + TIMER0_VAL_OFF);
return clocksource_mmio_init(timer_base + TPM_CNT,
timer_base = timer_of_base(&to_tpm);
counter_width = (readl(timer_base + TPM_PARAM)
writel(0, timer_base + TPM_SC);
writel(TPM_SC_TOF_MASK, timer_base + TPM_SC);
writel(0, timer_base + TPM_CNT);
writel(TPM_C0SC_CHF_MASK, timer_base + TPM_C0SC);
timer_base + TPM_SC);
writel(GENMASK(counter_width - 1, 0), timer_base + TPM_MOD);
static void __iomem *timer_base __ro_after_init;
val = readl(timer_base + TPM_C0SC);
writel(val, timer_base + TPM_C0SC);
val = readl(timer_base + TPM_C0SC);
writel(val, timer_base + TPM_C0SC);
writel(TPM_STATUS_CH0F, timer_base + TPM_STATUS);
return readl(timer_base + TPM_CNT);
writel(next, timer_base + TPM_C0V);
if ((next & 0xffffffff) != readl(timer_base + TPM_C0V))
timer_base = of_io_request_and_map(node, 0, "meson6-timer");
if (IS_ERR(timer_base)) {
val = readl(timer_base + MESON_ISA_TIMER_MUX);
writel(val, timer_base + MESON_ISA_TIMER_MUX);
clocksource_mmio_init(timer_base + MESON_ISA_TIMERE, node->name,
writel(val, timer_base + MESON_ISA_TIMER_MUX);
static void __iomem *timer_base;
return readl_relaxed(timer_base + MESON_ISA_TIMERE);
return (u64)readl(timer_base + MESON_ISA_TIMERE);
u32 val = readl(timer_base + MESON_ISA_TIMER_MUX);
timer_base + MESON_ISA_TIMER_MUX);
writel(delay, timer_base + MESON_ISA_TIMERA);
u32 val = readl(timer_base + MESON_ISA_TIMER_MUX);
timer_base + MESON_ISA_TIMER_MUX);
void __iomem *timer_base;
timer_base = of_iomap(np, 0);
if (!timer_base) {
pit_module_disable(timer_base);
ret = pit_clocksource_init(pit, name, timer_base, clk_rate);
ret = pit_clockevent_per_cpu_init(pit, name, timer_base, clk_rate, irq, pit_instances);
pit_module_enable(timer_base);
pit_module_disable(timer_base);
iounmap(timer_base);
timer_base = of_iomap(np, 0);
if (!timer_base) {
writel(~0, timer_base + TIMER0_VAL);
writel(~0, timer_base + TIMER0_RELOAD);
atomic_io_modify(timer_base + TIMER_CTRL,
ret = clocksource_mmio_init(timer_base + TIMER0_VAL,
static void __iomem *timer_base;
return ~readl(timer_base + TIMER0_VAL);
return ~readl(timer_base + TIMER0_VAL);
writel(delta, timer_base + TIMER1_VAL);
atomic_io_modify(timer_base + TIMER_CTRL,
atomic_io_modify(timer_base + TIMER_CTRL,
writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD);
writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL);
atomic_io_modify(timer_base + TIMER_CTRL,
ret = clocksource_mmio_init(timer_base + OSCR, "oscr0", clock_tick_rate, 200,
timer_base = of_iomap(np, 0);
if (!timer_base) {
timer_base = base;
#define timer_readl(reg) readl_relaxed(timer_base + (reg))
#define timer_writel(val, reg) writel_relaxed((val), timer_base + (reg))
static void __iomem *timer_base;
int timer_base[NR_TIMERS];
void __iomem *timer_base;
timer_base = base + timer->timer_base[i];
clkevt->base = timer_base;
clkevt->load = timer_base + timer->load;
clkevt->load_h = timer_base + timer->load_h;
clkevt->value = timer_base + timer->value;
clkevt->value_h = timer_base + timer->value_h;
clkevt->ctrl = timer_base + timer->ctrl;
clkevt->intclr = timer_base + timer->intclr;
timer1_base = base + timer->timer_base[0];
timer2_base = base + timer->timer_base[1];
.timer_base = {TIMER_1_BASE, TIMER_2_BASE},
.timer_base = {HISI_TIMER_1_BASE, HISI_TIMER_2_BASE},
void __iomem *timer_base;
timer_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(timer_base)) {
return PTR_ERR(timer_base);
st->base = timer_base;
unsigned int timer_base = devpriv->osc_base * prescale;
divisor = DIV_ROUND_UP(ns, timer_base);
divisor = ns / timer_base;
divisor = DIV_ROUND_CLOSEST(ns, timer_base);
static int dt3k_ns_to_timer(unsigned int timer_base, unsigned int *nanosec,
base = timer_base * (prescale + 1);
base = timer_base * (prescale + 1);
unsigned long timer_base = pci_resource_start(pcidev, 3);
if (!timer_base)
dev->pacer = comedi_8254_io_alloc(timer_base, 0, I8254_IO8, 0);
struct posix_cputimer_base *base = timer_base(timer, tsk);
base = timer_base(timer, p);
struct posix_cputimer_base *base = timer_base(timer, p);
struct timer_base *base, *new_base;
struct timer_base *new_base, *base;
struct timer_base *base;
struct timer_base *base;
static __init void timer_base_init_expiry_lock(struct timer_base *base)
static inline void timer_base_lock_expiry(struct timer_base *base)
static inline void timer_base_unlock_expiry(struct timer_base *base)
static void timer_sync_wait_running(struct timer_base *base)
struct timer_base *base = get_timer_base(tf);
static inline void timer_base_init_expiry_lock(struct timer_base *base) { }
static inline void timer_base_lock_expiry(struct timer_base *base) { }
static inline void timer_base_unlock_expiry(struct timer_base *base) { }
static inline void timer_sync_wait_running(struct timer_base *base) { }
static void expire_timers(struct timer_base *base, struct hlist_head *head)
static int collect_expired_timers(struct timer_base *base,
static int next_pending_bucket(struct timer_base *base, unsigned offset,
static void timer_recalc_next_expiry(struct timer_base *base)
static unsigned long next_timer_interrupt(struct timer_base *base,
struct timer_base *base_local,
struct timer_base *base_global,
struct timer_base *base_local, *base_global;
struct timer_base *base_local, *base_global;
struct timer_base *base_local, *base_global;
static void __run_timer_base(struct timer_base *base);
struct timer_base *base = per_cpu_ptr(&timer_bases[BASE_GLOBAL], cpu);
struct timer_base *base_local, *base_global;
static inline void __run_timers(struct timer_base *base)
static void __run_timer_base(struct timer_base *base)
struct timer_base *base = this_cpu_ptr(&timer_bases[index]);
struct timer_base *base = this_cpu_ptr(&timer_bases[BASE_LOCAL]);
static void migrate_timer_list(struct timer_base *new_base, struct hlist_head *head)
struct timer_base *base;
struct timer_base *old_base;
struct timer_base *new_base;
struct timer_base *base;
static DEFINE_PER_CPU(struct timer_base, timer_bases[NR_BASES]);
trigger_dyntick_cpu(struct timer_base *base, struct timer_list *timer)
static void enqueue_timer(struct timer_base *base, struct timer_list *timer,
static void internal_add_timer(struct timer_base *base, struct timer_list *timer)
static int detach_if_pending(struct timer_list *timer, struct timer_base *base,
static inline struct timer_base *get_timer_cpu_base(u32 tflags, u32 cpu)
static inline struct timer_base *get_timer_this_cpu_base(u32 tflags)
static inline struct timer_base *get_timer_base(u32 tflags)
static inline void __forward_timer_base(struct timer_base *base,
static inline void forward_timer_base(struct timer_base *base)
static struct timer_base *lock_timer_base(struct timer_list *timer,
struct timer_base *base;
struct ct_timer *atimer = ti->timer_base;
struct ct_timer *atimer = ti->timer_base;
struct ct_timer *timer_base;
ti->timer_base = atimer;
if (ti->timer_base->ops->prepare)
ti->timer_base->ops->prepare(ti);
struct ct_timer *atimer = ti->timer_base;
struct ct_timer *atimer = ti->timer_base;
struct ct_timer *atimer = ti->timer_base;