drivers/gpu/drm/tilcdc/tilcdc_crtc.c

120

tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

126

tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

148

tilcdc_set(dev, LCDC_RASTER_CTRL_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

185

tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

262

tilcdc_set(dev, LCDC_CLK_ENABLE_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

364

tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

402

tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

407

tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

412

tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

417

tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

422

tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

427

tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

476

tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

694

tilcdc_set(dev, LCDC_DMA_CTRL_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

697

tilcdc_set(dev, LCDC_INT_ENABLE_SET_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

972

tilcdc_set(dev, LCDC_RASTER_CTRL_REG,