ti_clk_ll_ops
struct ti_clk_ll_ops omap_clk_ll_ops = {
extern struct ti_clk_ll_ops omap_clk_ll_ops;
v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
v = ti_clk_ll_ops->clk_readl(&ad->autoidle_reg);
ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
val = ti_clk_ll_ops->clk_readl(&clk->reg);
ti_clk_ll_ops->clk_writel(val, &clk->reg);
val = ti_clk_ll_ops->clk_readl(&clk->reg);
ti_clk_ll_ops->clk_writel(val, &clk->reg);
int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops)
if (ti_clk_ll_ops) {
ti_clk_ll_ops = ops;
struct ti_clk_ll_ops *ti_clk_ll_ops;
ti_clk_ll_ops->clk_rmw(latch, latch, reg);
ti_clk_ll_ops->clk_rmw(0, latch, reg);
ti_clk_ll_ops->clk_readl(reg); /* OCP barrier */
ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
while (!_omap4_is_ready(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
while (!_omap4_is_idle(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
val = ti_clk_ll_ops->clk_readl(&hwclk->enable_reg);
r = ti_clk_ll_ops->cm_split_idlest_reg(&idlest_reg, &prcm_mod,
ti_clk_ll_ops->cm_wait_module_ready(0, prcm_mod, idlest_reg_id,
ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
v = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
ti_clk_ll_ops->clk_writel(v, &clk->enable_reg);
v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); /* OCP barrier */
v = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
ti_clk_ll_ops->clk_writel(v, &clk->enable_reg);
ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
v = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
if ((ti_clk_ll_ops->clk_readl(reg) & mask) == ena)
if (!(ti_clk_ll_ops->clk_readl(&companion_reg) &
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
v = ti_clk_ll_ops->clk_readl(&r);
ti_clk_ll_ops->clk_writel(v, &r);
v = ti_clk_ll_ops->clk_readl(&r);
ti_clk_ll_ops->clk_writel(v, &r);
extern struct ti_clk_ll_ops *ti_clk_ll_ops;
clkdm = ti_clk_ll_ops->clkdm_lookup(clk->clkdm_name);
ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
val = ti_clk_ll_ops->clk_readl(÷r->reg);
ti_clk_ll_ops->clk_writel(val, ÷r->reg);
val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift;
val = ti_clk_ll_ops->clk_readl(÷r->reg);
ti_clk_ll_ops->clk_writel(val, ÷r->reg);
val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift;
if ((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) ==
ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);
v = ti_clk_ll_ops->clk_readl(&dd->ssc_modfreq_reg);
ti_clk_ll_ops->clk_writel(v, &dd->ssc_modfreq_reg);
v = ti_clk_ll_ops->clk_readl(&dd->ssc_deltam_reg);
ti_clk_ll_ops->clk_writel(v, &dd->ssc_deltam_reg);
ti_clk_ll_ops->clk_writel(ctrl, &dd->control_reg);
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
r = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
while (((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask)
v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);
v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);
v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask;
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);
mult_div1 = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg);
ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg);
v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg);
ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg);
orig_v = ti_clk_ll_ops->clk_readl(&parent->reg);
ti_clk_ll_ops->clk_writel(dummy_v, &parent->reg);
ti_clk_ll_ops->clk_writel(orig_v, &parent->reg);
val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift;
val = ti_clk_ll_ops->clk_readl(&mux->reg);
ti_clk_ll_ops->clk_writel(val, &mux->reg);
int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops);