tg3_writephy
tg3_writephy(tp, MII_TG3_TEST1,
tg3_writephy(tp, MII_TG3_TEST1,
err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
return tg3_writephy(tp, MII_TG3_MISC_SHDW,
err = tg3_writephy(tp, MII_BMCR, phy_control);
tg3_writephy(tp, MII_BMCR,
tg3_writephy(tp, MII_TG3_FET_TEST,
tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
tg3_writephy(tp, MII_TG3_FET_TEST,
tg3_writephy(tp, reg, phy);
tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
tg3_writephy(tp, MII_BMCR,
tg3_writephy(tp, MII_CTRL1000,
tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
tg3_writephy(tp, MII_CTRL1000, phy9_orig);
tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
tg3_writephy(tp, MII_TG3_TEST1,
tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
tg3_writephy(tp, MII_TG3_EXT_CTRL,
tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
tg3_writephy(tp, MII_ADVERTISE, 0);
tg3_writephy(tp, MII_BMCR,
tg3_writephy(tp, MII_TG3_FET_TEST,
tg3_writephy(tp,
tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
tg3_writephy(tp, MII_TG3_EXT_CTRL,
tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
err = tg3_writephy(tp, MII_CTRL1000, new_adv);
tg3_writephy(tp, MII_BMCR,
tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
tg3_writephy(tp, MII_BMCR, bmcr);
tg3_writephy(tp, 0x15, 0x0a75);
tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
tg3_writephy(tp, MII_TG3_IMASK, ~0);
tg3_writephy(tp, MII_TG3_EXT_CTRL,
tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
tg3_writephy(tp, 0x16, 0x8007);
tg3_writephy(tp, MII_BMCR, BMCR_RESET);
tg3_writephy(tp, 0x10, 0x8411);
tg3_writephy(tp, 0x11, 0x0a10);
tg3_writephy(tp, 0x18, 0x00a0);
tg3_writephy(tp, 0x16, 0x41ff);
tg3_writephy(tp, 0x13, 0x0400);
tg3_writephy(tp, 0x13, 0x0000);
tg3_writephy(tp, 0x11, 0x0a50);
tg3_writephy(tp, 0x11, 0x0a10);
tg3_writephy(tp, 0x10, 0x8011);
tg3_writephy(tp, MII_ADVERTISE, newadv);
tg3_writephy(tp, MII_BMCR, bmcr);
tg3_writephy(tp, MII_ADVERTISE, adv);
tg3_writephy(tp, MII_BMCR, bmcr |
tg3_writephy(tp, MII_BMCR, new_bmcr);
tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
tg3_writephy(tp, MII_BMCR, bmcr);
tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
tg3_writephy(tp, MII_CTRL1000, val);
tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
tg3_writephy(tp, MII_BMCR, bmcr);
tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
tg3_writephy(tp, MII_TG3_EXT_CTRL,