drivers/gpu/drm/i915/display/dvo_tfp410.c

163

if (tfp410_readb(dvo, addr+0, &ch1) &&

drivers/gpu/drm/i915/display/dvo_tfp410.c

164

tfp410_readb(dvo, addr+1, &ch2))

drivers/gpu/drm/i915/display/dvo_tfp410.c

211

if (tfp410_readb(dvo, TFP410_CTL_2, &ctl2)) {

drivers/gpu/drm/i915/display/dvo_tfp410.c

244

if (!tfp410_readb(dvo, TFP410_CTL_1, &ctl1))

drivers/gpu/drm/i915/display/dvo_tfp410.c

259

if (!tfp410_readb(dvo, TFP410_CTL_1, &ctl1))

drivers/gpu/drm/i915/display/dvo_tfp410.c

272

tfp410_readb(dvo, TFP410_REV, &val);

drivers/gpu/drm/i915/display/dvo_tfp410.c

274

tfp410_readb(dvo, TFP410_CTL_1, &val);

drivers/gpu/drm/i915/display/dvo_tfp410.c

276

tfp410_readb(dvo, TFP410_CTL_2, &val);

drivers/gpu/drm/i915/display/dvo_tfp410.c

278

tfp410_readb(dvo, TFP410_CTL_3, &val);

drivers/gpu/drm/i915/display/dvo_tfp410.c

280

tfp410_readb(dvo, TFP410_USERCFG, &val);

drivers/gpu/drm/i915/display/dvo_tfp410.c

282

tfp410_readb(dvo, TFP410_DE_DLY, &val);

drivers/gpu/drm/i915/display/dvo_tfp410.c

284

tfp410_readb(dvo, TFP410_DE_CTL, &val);

drivers/gpu/drm/i915/display/dvo_tfp410.c

286

tfp410_readb(dvo, TFP410_DE_TOP, &val);

drivers/gpu/drm/i915/display/dvo_tfp410.c

288

tfp410_readb(dvo, TFP410_DE_CNT_LO, &val);

drivers/gpu/drm/i915/display/dvo_tfp410.c

289

tfp410_readb(dvo, TFP410_DE_CNT_HI, &val2);

drivers/gpu/drm/i915/display/dvo_tfp410.c

291

tfp410_readb(dvo, TFP410_DE_LIN_LO, &val);

drivers/gpu/drm/i915/display/dvo_tfp410.c

292

tfp410_readb(dvo, TFP410_DE_LIN_HI, &val2);

drivers/gpu/drm/i915/display/dvo_tfp410.c

294

tfp410_readb(dvo, TFP410_H_RES_LO, &val);

drivers/gpu/drm/i915/display/dvo_tfp410.c

295

tfp410_readb(dvo, TFP410_H_RES_HI, &val2);

drivers/gpu/drm/i915/display/dvo_tfp410.c

297

tfp410_readb(dvo, TFP410_V_RES_LO, &val);

drivers/gpu/drm/i915/display/dvo_tfp410.c

298

tfp410_readb(dvo, TFP410_V_RES_HI, &val2);