CSR_REGISTER_BASE
SCODE_100, CSR_REGISTER_BASE + CSR_BUS_MANAGER_ID, data,
CSR_REGISTER_BASE + CSR_STATE_SET,
if (a->offset < CSR_REGISTER_BASE + CSR_CONFIG_ROM_END)
CSR_REGISTER_BASE + CSR_BROADCAST_CHANNEL,
CSR_REGISTER_BASE + CSR_BROADCAST_CHANNEL,
u64 offset = (CSR_REGISTER_BASE | CSR_CONFIG_ROM) + index * 4;
i * 4 | CSR_REGISTER_BASE | CSR_CONFIG_ROM);
i * 4 | CSR_REGISTER_BASE | CSR_CONFIG_ROM);
CSR_REGISTER_BASE + CSR_BANDWIDTH_AVAILABLE,
offset = channel < 32 ? CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_HI :
CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_LO;
CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_HI,
CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_LO,
if ((offset != (CSR_REGISTER_BASE | CSR_FCP_COMMAND) &&
offset != (CSR_REGISTER_BASE | CSR_FCP_RESPONSE)) ||
{ .start = CSR_REGISTER_BASE | CSR_TOPOLOGY_MAP,
.end = CSR_REGISTER_BASE | CSR_TOPOLOGY_MAP_END, };
{ .start = CSR_REGISTER_BASE,
.end = CSR_REGISTER_BASE | CSR_CONFIG_ROM, };
int reg = offset & ~CSR_REGISTER_BASE;
{ .start = CSR_REGISTER_BASE,
.end = CSR_REGISTER_BASE | CSR_CONFIG_ROM_END, };
return offset >= (CSR_REGISTER_BASE | CSR_FCP_COMMAND) &&
offset + length <= (CSR_REGISTER_BASE | CSR_FCP_END);
csr = offset - CSR_REGISTER_BASE;
CSR_REGISTER_BASE + 4 * value;
CSR_REGISTER_BASE + CSR_BUSY_TIMEOUT, &d, 4);
.start = CSR_REGISTER_BASE + CSR_FCP_RESPONSE,
.end = CSR_REGISTER_BASE + CSR_FCP_END,
mgt_agt_addr = (tport->mgt_agt->handler.offset - CSR_REGISTER_BASE) / 4;
.start = CSR_REGISTER_BASE + 0x10000,
(CSR_REGISTER_BASE | CSR_CONFIG_ROM) + 3 * 4,
(CSR_REGISTER_BASE | CSR_CONFIG_ROM) + 4 * 4,
return CSR_REGISTER_BASE + CSR_IMPR;
return CSR_REGISTER_BASE + CSR_OMPR;
return CSR_REGISTER_BASE + CSR_IPCR(c->pcr_index);
return CSR_REGISTER_BASE + CSR_OPCR(c->pcr_index);
CSR_REGISTER_BASE + CSR_FCP_COMMAND,
.start = CSR_REGISTER_BASE + CSR_FCP_RESPONSE,
.end = CSR_REGISTER_BASE + CSR_FCP_END,
return CSR_REGISTER_BASE + value * 4;
#define OXFORD_FIRMWARE_ID_ADDRESS (CSR_REGISTER_BASE + 0x50000)
#define OXFORD_HARDWARE_ID_ADDRESS (CSR_REGISTER_BASE + 0x90020)