drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

42

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

585

const struct dcn_dpp_registers *tf_regs,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

595

dpp->tf_regs = tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1362

const struct dcn_dpp_registers *tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1523

const struct dcn_dpp_registers *tf_regs,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

43

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

163

if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) {

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

44

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

410

const struct dcn2_dpp_registers *tf_regs,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

42

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

420

dpp->tf_regs = tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

680

const struct dcn2_dpp_registers *tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

778

const struct dcn2_dpp_registers *tf_regs,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

37

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

301

const struct dcn201_dpp_registers *tf_regs,

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

311

dpp->tf_regs = tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

35

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h

60

const struct dcn201_dpp_registers *tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h

79

const struct dcn201_dpp_registers *tf_regs,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1527

const struct dcn3_dpp_registers *tf_regs,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1537

dpp->tf_regs = tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

34

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

563

const struct dcn3_dpp_registers *tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

583

const struct dcn3_dpp_registers *tf_regs,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

34

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

151

const struct dcn3_dpp_registers *tf_regs,

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

161

dpp->tf_regs = tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.h

34

const struct dcn3_dpp_registers *tf_regs,

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

131

uint32_t inst, const struct dcn3_dpp_registers *tf_regs,

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

135

bool ret = dpp32_construct(dpp, ctx, inst, tf_regs,

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

31

#define REG(reg) dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h

58

uint32_t inst, const struct dcn3_dpp_registers *tf_regs,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

266

const struct dcn401_dpp_registers *tf_regs,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

276

dpp->tf_regs = tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

36

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

669

const struct dcn401_dpp_registers *tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

698

const struct dcn401_dpp_registers *tf_regs,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

43

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

155

if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

44

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

354

static const struct dcn_dpp_registers tf_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

355

tf_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

356

tf_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

357

tf_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

358

tf_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

611

&tf_regs[inst], &tf_shift, &tf_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

420

static const struct dcn2_dpp_registers tf_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

421

tf_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

422

tf_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

423

tf_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

424

tf_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

425

tf_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

426

tf_regs(5),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

773

&tf_regs[inst], &tf_shift, &tf_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

469

static const struct dcn201_dpp_registers tf_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

470

tf_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

471

tf_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

472

tf_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

473

tf_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

642

&tf_regs[inst], &tf_shift, &tf_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

455

static const struct dcn2_dpp_registers tf_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

456

tf_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

457

tf_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

458

tf_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

459

tf_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

530

&tf_regs[inst], &tf_shift, &tf_mask))