t3_read_reg
status = t3_read_reg(phy->adapter,
t3_read_reg(phy->adapter,
t3_read_reg(phy->adapter,
t3_read_reg(phy->adapter,
t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
*p++ = t3_read_reg(ap, start);
t3_read_reg(adap, A_XGM_INT_STATUS +
t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
t3_read_reg(adapter, A_XGM_INT_STATUS +
cause = t3_read_reg(adapter, A_XGM_INT_CAUSE + mac->offset);
status = t3_read_reg(adapter, A_SG_INT_CAUSE);
v = (t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS) >> S_FL0EMPTY) &
t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
t3_read_reg(adapter, A_PCIE_PEX_ERR));
v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
uiip->llimit = t3_read_reg(adapter, A_ULPRX_ISCSI_LLIMIT);
uiip->ulimit = t3_read_reg(adapter, A_ULPRX_ISCSI_ULIMIT);
uiip->tagmask = t3_read_reg(adapter, A_ULPRX_ISCSI_TAGMASK);
val = t3_read_reg(adapter, A_ULPRX_ISCSI_PSZ);
val = t3_read_reg(adapter, A_TP_PARA_REG7);
t3_read_reg(adapter, A_PM1_TX_CFG) >> 17);
val = t3_read_reg(adapter, A_TP_PARA_REG2);
((t3_read_reg(adapter, A_TP_PARA_REG2)) >>
if (val && (val != t3_read_reg(adapter, A_ULPRX_ISCSI_PSZ))) {
t3_read_reg(adapter, A_ULPTX_TPT_LLIMIT);
rdma->tpt_top = t3_read_reg(adapter, A_ULPTX_TPT_ULIMIT);
t3_read_reg(adapter, A_ULPTX_PBL_LLIMIT);
rdma->pbl_top = t3_read_reg(adapter, A_ULPTX_PBL_ULIMIT);
rdma->rqt_base = t3_read_reg(adapter, A_ULPRX_RQ_LLIMIT);
rdma->rqt_top = t3_read_reg(adapter, A_ULPRX_RQ_ULIMIT);
ddpp->llimit = t3_read_reg(adapter, A_ULPRX_TDDP_LLIMIT);
ddpp->ulimit = t3_read_reg(adapter, A_ULPRX_TDDP_ULIMIT);
ddpp->tag_mask = t3_read_reg(adapter, A_ULPRX_TDDP_TAGMASK);
unsigned int server_base = t3_read_reg(adap, A_MC5_DB_SERVER_INDEX);
cfg = t3_read_reg(adap, A_MC5_DB_CONFIG) & ~F_TMMODE;
u32 cause = t3_read_reg(adap, A_MC5_DB_INT_CAUSE);
u32 cfg = t3_read_reg(adapter, A_MC5_DB_CONFIG);
t3_read_reg(adap, A_PL_CLI); /* flush */
map = t3_read_reg(adap, A_SG_DATA_INTR);
map = t3_read_reg(adap, A_SG_DATA_INTR);
unsigned int v, status = t3_read_reg(adapter, A_SG_INT_CAUSE) &
v = t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS);
status = t3_read_reg(adap, A_SG_RSPQ_FL_STATUS);
u32 v = t3_read_reg(adapter, addr) & ~mask;
t3_read_reg(adapter, addr); /* flush */
if (t3_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
*valp++ = t3_read_reg(adap, A_CIM_HOST_ACC_DATA);
*rx_cfg = t3_read_reg(mac->adapter, A_XGM_RX_CFG);
*rx_hash_high = t3_read_reg(mac->adapter, A_XGM_RX_HASH_HIGH);
*rx_hash_low = t3_read_reg(mac->adapter, A_XGM_RX_HASH_LOW);
status = t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset);
link_fault = t3_read_reg(adapter,
*vals++ = t3_read_reg(adap, data_reg);
unsigned int status = t3_read_reg(adapter, reg) & mask;
if (t3_read_reg(adapter, A_PCIE_INT_CAUSE) & F_PEXERR)
t3_read_reg(adapter, A_PCIE_PEX_ERR));
val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP);
val = t3_read_reg(adap,
u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE);
t3_read_reg(adapter, mc7->offset + A_MC7_CE_ADDR),
t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA0),
t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA1),
t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA2));
t3_read_reg(adapter, mc7->offset + A_MC7_UE_ADDR),
t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA0),
t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA1),
t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA2));
val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1);
addr = t3_read_reg(adapter,
val64 = t3_read_reg(adap,
u32 cause = t3_read_reg(adap, A_XGM_INT_CAUSE + mac->offset) &
u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE);
u32 cause = t3_read_reg(adapter, A_PL_INT_CAUSE0);
t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
t3_read_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx)); /* flush */
t3_read_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx)); /* flush */
t3_read_reg(adapter, XGM_REG(A_XGM_INT_CAUSE, idx)); /* flush */
if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
ret = t3_read_reg(adapter, A_MI1_DATA);
if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
return G_CQ_INDEX(t3_read_reg(adapter, A_SG_CONTEXT_DATA0));
val = t3_read_reg(adap, A_TP_PARA_REG3);
ret = t3_read_reg(adapter, A_MI1_DATA);
t3_read_reg(adapter, A_TP_PIO_DATA);
v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
t3_read_reg(adapter, A_XGM_XAUI_IMP);
v = t3_read_reg(adapter, A_XGM_XAUI_IMP);
t3_read_reg(adapter, addr); /* flush */
if (!(t3_read_reg(adapter, addr) & F_BUSY))
val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
t3_read_reg(adapter, mc7->offset + A_MC7_CAL);
if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) &
t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
t3_read_reg(adapter, mc7->offset + A_MC7_REF); /* flush */
t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */
val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP);
fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0));
G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE));
t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */
} while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts);
pci_mode = t3_read_reg(adapter, A_PCIX_MODE);
cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
t3_read_reg(adapter, A_XGM_PORT_CFG);
t3_read_reg(adapter, A_XGM_PORT_CFG);
t3_read_reg(adapter, A_XGM_PORT_CFG);
if (t3_read_reg(adap, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
adapter->params.rev = t3_read_reg(adapter, A_PL_REV);
u32 val = t3_read_reg(adapter, reg);
if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
*valp = t3_read_reg(adapter, A_SF_DATA);
if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
*vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
store = t3_read_reg(adap, A_TP_TX_DROP_CFG_CH0 + idx);
t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
u32 v = t3_read_reg(mac->adapter, reg);
t3_read_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1); /* flush */
u32 v = t3_read_reg(mac->adapter, reg);
t3_read_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1); /* flush */
val = t3_read_reg(adap, A_XGM_RX_CFG + oft) & ~F_COPYALLFRAMES;
(t3_read_reg(adap, A_XGM_RX_CTRL + mac->offset) & F_RXEN)) {
v = t3_read_reg(adap, A_XGM_RX_CFG + mac->offset);
v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset);
val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
G_RXMAXPKTSIZE(t3_read_reg(adap,
mac->tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
mac->tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
mac->rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */
t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */
#define RMON_READ(mac, addr) t3_read_reg(mac->adapter, addr + mac->offset)
t3_read_reg(adap, ctrl);
v = t3_read_reg(mac->adapter, A_TP_MIB_RDATA);