tegra_vde_writel
tegra_vde_writel(vde, 0xA0000000 | (reg << 24) | (val & 0xFFFF),
tegra_vde_writel(vde, 0xA0000000 | ((reg + 1) << 24) | (val >> 16),
tegra_vde_writel(vde, value, vde->bsev, ICMDQUE_WR);
tegra_vde_writel(vde, y_addr >> 8, vde->frameid, 0x000 + frameid * 4);
tegra_vde_writel(vde, cb_addr >> 8, vde->frameid, 0x100 + frameid * 4);
tegra_vde_writel(vde, cr_addr >> 8, vde->frameid, 0x180 + frameid * 4);
tegra_vde_writel(vde, value1, vde->frameid, 0x080 + frameid * 4);
tegra_vde_writel(vde, value2, vde->frameid, 0x280 + frameid * 4);
tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x1C);
tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x00);
tegra_vde_writel(vde, 0x00000007, vde->vdma, 0x04);
tegra_vde_writel(vde, 0x00000007, vde->frameid, 0x200);
tegra_vde_writel(vde, 0x00000005, vde->tfe, 0x04);
tegra_vde_writel(vde, 0x00000000, vde->mbe, 0x84);
tegra_vde_writel(vde, 0x00000010, vde->sxe, 0x08);
tegra_vde_writel(vde, 0x00000150, vde->sxe, 0x54);
tegra_vde_writel(vde, 0x0000054C, vde->sxe, 0x58);
tegra_vde_writel(vde, 0x00000E34, vde->sxe, 0x5C);
tegra_vde_writel(vde, 0x063C063C, vde->mce, 0x10);
tegra_vde_writel(vde, 0x0003FC00, vde->bsev, INTR_STATUS);
tegra_vde_writel(vde, 0x0000150D, vde->bsev, BSE_CONFIG);
tegra_vde_writel(vde, 0x00000100, vde->bsev, BSE_INT_ENB);
tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x98);
tegra_vde_writel(vde, 0x00000060, vde->bsev, 0x9C);
tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x8C);
tegra_vde_writel(vde, bitstream_data_addr + bitstream_data_size,
tegra_vde_writel(vde, value, vde->bsev, 0x88);
tegra_vde_writel(vde, value, vde->sxe, 0x10);
tegra_vde_writel(vde, value, vde->sxe, 0x40);
tegra_vde_writel(vde, value, vde->sxe, 0x44);
tegra_vde_writel(vde, value, vde->sxe, 0x48);
tegra_vde_writel(vde, value, vde->sxe, 0x4C);
tegra_vde_writel(vde, value, vde->sxe, 0x68);
tegra_vde_writel(vde, bitstream_data_addr, vde->sxe, 0x6C);
tegra_vde_writel(vde, vde->secure_bo->dma_addr, vde->sxe, 0x7c);
tegra_vde_writel(vde, value, vde->mbe, 0x80);
tegra_vde_writel(vde, value, vde->mbe, 0x80);
tegra_vde_writel(vde, 0xF4000001, vde->mbe, 0x80);
tegra_vde_writel(vde, 0x20000000, vde->mbe, 0x80);
tegra_vde_writel(vde, 0xF4000101, vde->mbe, 0x80);
tegra_vde_writel(vde, value, vde->mbe, 0x80);
tegra_vde_writel(vde, value, vde->mbe, 0x80);
tegra_vde_writel(vde, 0x00000001, vde->bsev, 0x8C);
tegra_vde_writel(vde, 0x20000000 | (macroblocks_nb - 1),
tegra_vde_writel(vde, 0xD0000000 | (0 << 23), vde->mbe, 0x80);
tegra_vde_writel(vde, 0xD0200000 | (0 << 23), vde->mbe, 0x80);
tegra_vde_writel(vde, 0xD0000000 | (frame_idx << 23),
tegra_vde_writel(vde, 0xD0200000 | (frame_idx << 23),
tegra_vde_writel(vde, value, vde->mbe, 0x80);
tegra_vde_writel(vde, value | mask, base, offset);
void tegra_vde_writel(struct tegra_vde *vde, u32 value, void __iomem *base,