tegra_spi_writel
tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
tegra_spi_writel(tspi, tspi->def_command2_reg, SPI_COMMAND2);
tegra_spi_writel(tspi, val, SPI_TRANS_STATUS);
tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR,
tegra_spi_writel(tspi, x, SPI_TX_FIFO);
tegra_spi_writel(tspi, x, SPI_TX_FIFO);
tegra_spi_writel(tspi, status, SPI_FIFO_STATUS);
tegra_spi_writel(tspi, val, SPI_DMA_BLK);
tegra_spi_writel(tspi, val, SPI_DMA_CTL);
tegra_spi_writel(tspi, val, SPI_DMA_CTL);
tegra_spi_writel(tspi, val, SPI_DMA_BLK);
tegra_spi_writel(tspi, val, SPI_DMA_CTL);
tegra_spi_writel(tspi, val, SPI_COMMAND1);
tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING1);
tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING2);
tegra_spi_writel(tspi, command1, SPI_COMMAND1);
tegra_spi_writel(tspi, command1, SPI_COMMAND1);
tegra_spi_writel(tspi, command2, SPI_COMMAND2);
tegra_spi_writel(tspi, command1, SPI_COMMAND1);
tegra_spi_writel(tspi, val, SPI_INTR_MASK);
tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);