tegra_spi_readl
tegra_spi_readl(tspi, SPI_COMMAND1),
tegra_spi_readl(tspi, SPI_COMMAND2));
tegra_spi_readl(tspi, SPI_DMA_CTL),
tegra_spi_readl(tspi, SPI_DMA_BLK));
tegra_spi_readl(tspi, SPI_TRANS_STATUS),
tegra_spi_readl(tspi, SPI_FIFO_STATUS));
tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1);
tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2);
tspi->def_command2_reg = tegra_spi_readl(tspi, SPI_COMMAND2);
tegra_spi_readl(tspi, SPI_COMMAND1);
val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
val = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO);
u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask;
status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
val = tegra_spi_readl(tspi, SPI_INTR_MASK);