tegra_sor_writel
tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
tegra_sor_writel(sor, value, SOR_PWR);
tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
tegra_sor_writel(sor, value, SOR_STATE1);
tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
tegra_sor_writel(sor, value, SOR_PWR);
tegra_sor_writel(sor, value, sor->soc->regs->pll2);
tegra_sor_writel(sor, value, sor->soc->regs->pll0);
tegra_sor_writel(sor, value, sor->soc->regs->pll2);
tegra_sor_writel(sor, value, SOR_STATE1);
tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
tegra_sor_writel(sor, value, SOR_TEST);
tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
tegra_sor_writel(sor, value, offset);
tegra_sor_writel(sor, value, offset++);
tegra_sor_writel(sor, value, offset++);
tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
tegra_sor_writel(sor, value, SOR_INT_ENABLE);
tegra_sor_writel(sor, value, SOR_INT_MASK);
tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
tegra_sor_writel(sor, 0, SOR_INT_MASK);
tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
tegra_sor_writel(sor, 0, SOR_STATE1);
tegra_sor_writel(sor, value, sor->soc->regs->pll2);
tegra_sor_writel(sor, value, sor->soc->regs->pll3);
tegra_sor_writel(sor, value, sor->soc->regs->pll0);
tegra_sor_writel(sor, value, sor->soc->regs->pll2);
tegra_sor_writel(sor, value, sor->soc->regs->pll2);
tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
tegra_sor_writel(sor, value, SOR_DP_SPARE0);
tegra_sor_writel(sor, value, SOR_SEQ_CTL);
tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
tegra_sor_writel(sor, value, SOR_REFCLK);
tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
tegra_sor_writel(sor, value, SOR_STATE1);
tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
tegra_sor_writel(sor, value, sor->soc->regs->pll0);
tegra_sor_writel(sor, value, sor->soc->regs->pll1);
tegra_sor_writel(sor, value, sor->soc->regs->pll3);
tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
tegra_sor_writel(sor, value, SOR_STATE1);
tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
tegra_sor_writel(sor, value, SOR_DP_SPARE0);
tegra_sor_writel(sor, 0, SOR_STATE1);
tegra_sor_writel(sor, value, SOR_STATE1);
tegra_sor_writel(sor, value, sor->soc->regs->pll2);
tegra_sor_writel(sor, value, sor->soc->regs->pll3);
tegra_sor_writel(sor, value, sor->soc->regs->pll0);
tegra_sor_writel(sor, value, sor->soc->regs->pll2);
tegra_sor_writel(sor, value, sor->soc->regs->pll2);
tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
tegra_sor_writel(sor, value, SOR_DP_SPARE0);
tegra_sor_writel(sor, 0, SOR_LVDS);
tegra_sor_writel(sor, value, sor->soc->regs->pll0);
tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
tegra_sor_writel(sor, value, SOR_STATE1);
tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
tegra_sor_writel(sor, value, SOR_CSTM);
tegra_sor_writel(sor, value, SOR_INT_STATUS);
tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
tegra_sor_writel(sor, value, sor->soc->regs->pll1);
tegra_sor_writel(sor, value, sor->soc->regs->pll1);
tegra_sor_writel(sor, value, sor->soc->regs->pll1);
tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0);
tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0);
tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0);
tegra_sor_writel(sor, pattern, SOR_DP_TPG);
tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
tegra_sor_writel(sor, value, sor->soc->regs->pll1);
tegra_sor_writel(sor, value, SOR_DP_SPARE0);
tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
tegra_sor_writel(sor, 0, SOR_STATE0);
tegra_sor_writel(sor, 1, SOR_STATE0);
tegra_sor_writel(sor, 0, SOR_STATE0);
tegra_sor_writel(sor, value, SOR_PWM_DIV);
tegra_sor_writel(sor, value, SOR_PWM_CTL);