arch/riscv/include/asm/kvm_vcpu_pmu.h

115

if (csr_num == CSR_CYCLE || csr_num == CSR_INSTRET) {

arch/riscv/include/asm/kvm_vcpu_pmu.h

124

{.base = CSR_CYCLE, .count = 3, .func = kvm_riscv_vcpu_pmu_read_legacy },

arch/riscv/include/asm/kvm_vcpu_pmu.h

69

{.base = CSR_CYCLE, .count = 32, .func = kvm_riscv_vcpu_pmu_read_hpm },

arch/riscv/include/asm/kvm_vcpu_pmu.h

72

{.base = CSR_CYCLE, .count = 32, .func = kvm_riscv_vcpu_pmu_read_hpm },

arch/riscv/kvm/vcpu_pmu.c

379

if (csr_num == CSR_CYCLE || csr_num == CSR_INSTRET) {

arch/riscv/kvm/vcpu_pmu.c

391

cidx = csr_num - CSR_CYCLE;

arch/riscv/kvm/vcpu_pmu.c

877

pmc->cinfo.csr = CSR_CYCLE + i;

drivers/perf/riscv_pmu.c

116

switchcase_csr_read_32(CSR_CYCLE, ret)

drivers/perf/riscv_pmu.c

136

if (csr < CSR_CYCLE || csr > CSR_HPMCOUNTER31H ||

drivers/perf/riscv_pmu_legacy.c

53

val = riscv_pmu_ctr_read_csr(CSR_CYCLE);

drivers/perf/riscv_pmu_sbi.c

1110

hidx = info->csr - CSR_CYCLE;

drivers/perf/riscv_pmu_sbi.c

499

if (!hpm_width && info->csr != CSR_CYCLE && info->csr != CSR_INSTRET)

drivers/perf/riscv_pmu_sbi.c

514

return pmu_ctr_list[event->hw.idx].csr - CSR_CYCLE;

drivers/perf/riscv_pmu_sbi.c

561

cmask = BIT(CSR_INSTRET - CSR_CYCLE);

tools/lib/perf/mmap.c

451

switchcase_csr_read_32(CSR_CYCLE, ret)

tools/lib/perf/mmap.c

467

return csr_read_num(CSR_CYCLE + counter);

tools/testing/selftests/kvm/riscv/sbi_pmu_test.c

151

__GUEST_ASSERT((csr_num >= CSR_CYCLE && csr_num <= CSR_HPMCOUNTER31),

tools/testing/selftests/kvm/riscv/sbi_pmu_test.c

75

switchcase_csr_read_32(CSR_CYCLE, ret)