arch/x86/kvm/svm/avic.c

138

svm_set_intercept_for_msr(vcpu, APIC_BASE_MSR + i,

arch/x86/kvm/svm/avic.c

141

svm_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_W, intercept);

arch/x86/kvm/svm/avic.c

142

svm_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W, intercept);

arch/x86/kvm/svm/avic.c

143

svm_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W, intercept);

arch/x86/kvm/svm/avic.c

144

svm_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_ICR), MSR_TYPE_W, intercept);

arch/x86/kvm/svm/sev.c

4651

svm_set_intercept_for_msr(vcpu, MSR_TSC_AUX, MSR_TYPE_RW,

arch/x86/kvm/svm/sev.c

4655

svm_set_intercept_for_msr(vcpu, MSR_AMD64_GUEST_TSC_FREQ, MSR_TYPE_R,

arch/x86/kvm/svm/sev.c

4670

svm_set_intercept_for_msr(vcpu, MSR_IA32_XSS, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

741

svm_set_intercept_for_msr(vcpu, MSR_IA32_LASTBRANCHFROMIP, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

742

svm_set_intercept_for_msr(vcpu, MSR_IA32_LASTBRANCHTOIP, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

743

svm_set_intercept_for_msr(vcpu, MSR_IA32_LASTINTFROMIP, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

744

svm_set_intercept_for_msr(vcpu, MSR_IA32_LASTINTTOIP, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

747

svm_set_intercept_for_msr(vcpu, MSR_IA32_DEBUGCTLMSR, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

768

svm_set_intercept_for_msr(vcpu, MSR_K7_PERFCTR0 + i,

arch/x86/kvm/svm/svm.c

773

svm_set_intercept_for_msr(vcpu, MSR_F15H_PERF_CTR + 2 * i,

arch/x86/kvm/svm/svm.c

781

svm_set_intercept_for_msr(vcpu, MSR_AMD64_PERF_CNTR_GLOBAL_CTL,

arch/x86/kvm/svm/svm.c

783

svm_set_intercept_for_msr(vcpu, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS,

arch/x86/kvm/svm/svm.c

785

svm_set_intercept_for_msr(vcpu, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR,

arch/x86/kvm/svm/svm.c

787

svm_set_intercept_for_msr(vcpu, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET,

arch/x86/kvm/svm/svm.c

811

svm_set_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W,

arch/x86/kvm/svm/svm.c

815

svm_set_intercept_for_msr(vcpu, MSR_IA32_FLUSH_CMD, MSR_TYPE_W,

arch/x86/kvm/svm/svm.c

825

svm_set_intercept_for_msr(vcpu, MSR_IA32_SPEC_CTRL, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

828

svm_set_intercept_for_msr(vcpu, MSR_IA32_SPEC_CTRL, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

835

svm_set_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

837

svm_set_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

848

svm_set_intercept_for_msr(vcpu, MSR_IA32_U_CET, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

849

svm_set_intercept_for_msr(vcpu, MSR_IA32_S_CET, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

850

svm_set_intercept_for_msr(vcpu, MSR_IA32_PL0_SSP, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

851

svm_set_intercept_for_msr(vcpu, MSR_IA32_PL1_SSP, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

852

svm_set_intercept_for_msr(vcpu, MSR_IA32_PL2_SSP, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

853

svm_set_intercept_for_msr(vcpu, MSR_IA32_PL3_SSP, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.h

825

void svm_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type, bool set);

arch/x86/kvm/svm/svm.h

830

svm_set_intercept_for_msr(vcpu, msr, type, false);

arch/x86/kvm/svm/svm.h

836

svm_set_intercept_for_msr(vcpu, msr, type, true);