tegra_qspi_writel
tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1);
tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1);
tegra_qspi_writel(tqspi, status, QSPI_TRANS_STATUS);
tegra_qspi_writel(tqspi, value, QSPI_DMA_CTL);
tegra_qspi_writel(tqspi, value, QSPI_COMMAND1);
tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
tegra_qspi_writel(tqspi, cmd_value, QSPI_CMB_SEQ_CMD);
tegra_qspi_writel(tqspi, address_value,
tegra_qspi_writel(tqspi, cmd_config,
tegra_qspi_writel(tqspi, addr_config,
tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1);
tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1);
tegra_qspi_writel(tqspi, tqspi->def_command2_reg, QSPI_COMMAND2);
tegra_qspi_writel(tqspi, value, QSPI_TRANS_STATUS);
tegra_qspi_writel(tqspi, value, QSPI_INTR_MASK);
tegra_qspi_writel(tqspi, QSPI_ERR | QSPI_FIFO_ERROR, QSPI_FIFO_STATUS);
tegra_qspi_writel(tqspi, x, QSPI_TX_FIFO);
tegra_qspi_writel(tqspi, x, QSPI_TX_FIFO);
tegra_qspi_writel(tqspi, val, QSPI_FIFO_STATUS);
tegra_qspi_writel(tqspi, intr_mask, QSPI_INTR_MASK);
tegra_qspi_writel(tqspi, val, QSPI_DMA_BLK);
tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL);
tegra_qspi_writel(tqspi, lower_32_bits(tx_dma_phys),
tegra_qspi_writel(tqspi, (upper_32_bits(tx_dma_phys) & 0xff),
tegra_qspi_writel(tqspi, lower_32_bits(rx_dma_phys),
tegra_qspi_writel(tqspi, (upper_32_bits(rx_dma_phys) & 0xff),
tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1);
tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL);
tegra_qspi_writel(qspi, val, QSPI_DMA_BLK);
tegra_qspi_writel(qspi, val, QSPI_COMMAND1);
tegra_qspi_writel(tqspi, command1, QSPI_COMMAND1);
tegra_qspi_writel(tqspi, command2, QSPI_COMMAND2);
tegra_qspi_writel(tqspi, command1, QSPI_COMMAND1);
tegra_qspi_writel(tqspi, QSPI_NUM_DUMMY_CYCLE(tqspi->dummy_cycles), QSPI_MISC_REG);
tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1);