tegra_pmc_writel
tegra_pmc_writel(pmc, value, PMC_CNTRL);
tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37);
tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
tegra_pmc_writel(pmc, value, PMC_PWR_DET);
tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
tegra_pmc_writel(pmc, value, PMC_CNTRL);
tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
tegra_pmc_writel(pmc, value, offset);
tegra_pmc_writel(pmc, value, offset);
tegra_pmc_writel(clk->pmc, val, clk->offs);
tegra_pmc_writel(pmc, val, offs);
tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
tegra_pmc_writel(pmc, value, offset);
tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
tegra_pmc_writel(pmc, value, PMC_CNTRL);
tegra_pmc_writel(pmc, value, PMC_CNTRL);
tegra_pmc_writel(pmc, value, PMC_CNTRL);
tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
tegra_pmc_writel(pmc, value, PMC_CNTRL);
tegra_pmc_writel(pmc, value, offset);
tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);