tegra_pmc_readl
value = tegra_pmc_readl(pmc, PMC_CNTRL);
value = tegra_pmc_readl(pmc, offset);
value = tegra_pmc_readl(pmc, status);
value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
value = tegra_pmc_readl(pmc, PMC_PWR_DET);
value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
value = tegra_pmc_readl(pmc, PMC_CNTRL);
value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
value = tegra_pmc_readl(pmc, offset);
value = tegra_pmc_readl(pmc, offset);
tegra_pmc_readl(pmc, offset);
val = tegra_pmc_readl(clk->pmc, clk->offs) >> clk->mux_shift;
val = tegra_pmc_readl(clk->pmc, clk->offs);
val = tegra_pmc_readl(clk->pmc, clk->offs) & BIT(clk->force_en_shift);
val = tegra_pmc_readl(pmc, offs);
u32 value = tegra_pmc_readl(gate->pmc, gate->offs);
*value = tegra_pmc_readl(pmc, offset);
value = tegra_pmc_readl(pmc, PMC_CNTRL);
value = tegra_pmc_readl(pmc, PMC_CNTRL);
value = tegra_pmc_readl(pmc, PMC_CNTRL);
value = tegra_pmc_readl(pmc, PMC_CNTRL);
return tegra_pmc_readl(pmc, offset);
return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START);