CSR_BIT
#define FBNIC_QUEUE_TWQ_CTL_RESET CSR_BIT(0)
#define FBNIC_QUEUE_TWQ_CTL_ENABLE CSR_BIT(1)
#define FBNIC_QUEUE_TCQ_CTL_RESET CSR_BIT(0)
#define FBNIC_QUEUE_TCQ_CTL_ENABLE CSR_BIT(1)
#define FBNIC_QUEUE_TIM_CLEAR_MASK CSR_BIT(0)
#define FBNIC_QUEUE_TIM_SET_MASK CSR_BIT(0)
#define FBNIC_QUEUE_TIM_MASK_MASK CSR_BIT(0)
#define FBNIC_QUEUE_RCQ_CTL_RESET CSR_BIT(0)
#define FBNIC_QUEUE_RCQ_CTL_ENABLE CSR_BIT(1)
#define FBNIC_QUEUE_BDQ_CTL_RESET CSR_BIT(0)
#define FBNIC_QUEUE_BDQ_CTL_ENABLE CSR_BIT(1)
#define FBNIC_QUEUE_BDQ_CTL_PPQ_ENABLE CSR_BIT(30)
#define FBNIC_QUEUE_RDE_CTL0_EN_HDR_SPLIT CSR_BIT(31)
#define FBNIC_QUEUE_RIM_CLEAR_MASK CSR_BIT(0)
#define FBNIC_QUEUE_RIM_SET_MASK CSR_BIT(0)
#define FBNIC_QUEUE_RIM_MASK_MASK CSR_BIT(0)
#define FBNIC_INTR_MSIX_CTRL_ENABLE CSR_BIT(31)
#define FBNIC_INTR_CQ_REARM_RCQ_TIMEOUT_UPD_EN CSR_BIT(14)
#define FBNIC_INTR_CQ_REARM_TCQ_TIMEOUT_UPD_EN CSR_BIT(29)
#define FBNIC_INTR_CQ_REARM_INTR_RELOAD CSR_BIT(30)
#define FBNIC_INTR_CQ_REARM_INTR_UNMASK CSR_BIT(31)
#define FBNIC_QM_TQS_CTL0_LSO_TS_MASK CSR_BIT(0)
#define FBNIC_QM_TNI_TDE_CTL_MRRS_1K CSR_BIT(25)
#define FBNIC_TCE_LSO_CTRL_IPID_MODE_INC CSR_BIT(27)
#define FBNIC_TCE_CSO_CTRL_TCP_ZERO_CSUM CSR_BIT(0)
#define FBNIC_TCE_TXB_CTRL_LOAD CSR_BIT(0)
#define FBNIC_TCE_TXB_CTRL_TCAM_ENABLE CSR_BIT(1)
#define FBNIC_TCE_TXB_CTRL_DISABLE CSR_BIT(2)
#define FBNIC_TCE_DROP_CTRL_TTI_CM_DROP_EN CSR_BIT(0)
#define FBNIC_TCE_DROP_CTRL_TTI_FRM_DROP_EN CSR_BIT(1)
#define FBNIC_TCE_DROP_CTRL_TTI_TBI_DROP_EN CSR_BIT(2)
#define FBNIC_TCE_RAM_TCAM3_MCQ_MASK CSR_BIT(7)
#define FBNIC_TCE_RAM_TCAM3_VALIDATE CSR_BIT(31)
#define FBNIC_TMI_DROP_CTRL_EN CSR_BIT(0)
#define FBNIC_PTP_CTRL_EN CSR_BIT(0)
#define FBNIC_PTP_CTRL_MONO_EN CSR_BIT(4)
#define FBNIC_PTP_CTRL_TQS_OUT_EN CSR_BIT(8)
#define FBNIC_PTP_ADJUST_INIT CSR_BIT(0)
#define FBNIC_PTP_ADJUST_SUB_NUDGE CSR_BIT(8)
#define FBNIC_PTP_ADJUST_ADD_NUDGE CSR_BIT(16)
#define FBNIC_PTP_ADJUST_ADDEND_SET CSR_BIT(24)
#define FBNIC_RXB_CT_SIZE_ENABLE CSR_BIT(12)
#define FBNIC_RPC_RMI_CONFIG_FCS_PRESENT CSR_BIT(8)
#define FBNIC_RPC_RMI_CONFIG_ENABLE CSR_BIT(12)
#define FBNIC_RPC_ACT_TBL0_DROP CSR_BIT(0)
#define FBNIC_RPC_ACT_TBL0_Q_SEL CSR_BIT(4)
#define FBNIC_RPC_ACT_TBL0_TS_ENA CSR_BIT(28)
#define FBNIC_RPC_ACT_TBL0_ACT_TBL_IDX CSR_BIT(29)
#define FBNIC_RPC_ACT_TBL0_RSS_CTXT_ID CSR_BIT(30)
#define FBNIC_RPC_TCAM_VALIDATE CSR_BIT(31)
#define FBNIC_FAB_AXI4_AR_SPACER_MASK CSR_BIT(16)
#define FBNIC_MAC_COMMAND_CONFIG_RX_PAUSE_DIS CSR_BIT(29)
#define FBNIC_MAC_COMMAND_CONFIG_TX_PAUSE_DIS CSR_BIT(28)
#define FBNIC_MAC_COMMAND_CONFIG_FLT_HDL_DIS CSR_BIT(27)
#define FBNIC_MAC_COMMAND_CONFIG_TX_PAD_EN CSR_BIT(11)
#define FBNIC_MAC_COMMAND_CONFIG_LOOPBACK_EN CSR_BIT(10)
#define FBNIC_MAC_COMMAND_CONFIG_PROMISC_EN CSR_BIT(4)
#define FBNIC_MAC_COMMAND_CONFIG_RX_ENA CSR_BIT(1)
#define FBNIC_MAC_COMMAND_CONFIG_TX_ENA CSR_BIT(0)
#define FBNIC_SIG_MAC_IN0_RESET_FF_TX_CLK CSR_BIT(14)
#define FBNIC_SIG_MAC_IN0_RESET_FF_RX_CLK CSR_BIT(13)
#define FBNIC_SIG_MAC_IN0_RESET_TX_CLK CSR_BIT(12)
#define FBNIC_SIG_MAC_IN0_RESET_RX_CLK CSR_BIT(11)
#define FBNIC_SIG_MAC_IN0_TX_CRC CSR_BIT(8)
#define FBNIC_SIG_MAC_IN0_CFG_MODE128 CSR_BIT(10)
#define FBNIC_SIG_PCS_OUT0_LINK CSR_BIT(27)
#define FBNIC_SIG_PCS_INTR_LINK_DOWN CSR_BIT(1)
#define FBNIC_SIG_PCS_INTR_LINK_UP CSR_BIT(0)
#define FBNIC_PUL_OB_TLP_HDR_AW_CFG_FLUSH CSR_BIT(19)
#define FBNIC_PUL_OB_TLP_HDR_AW_CFG_BME CSR_BIT(18)
#define FBNIC_PUL_OB_TLP_HDR_AR_CFG_FLUSH CSR_BIT(19)
#define FBNIC_PUL_OB_TLP_HDR_AR_CFG_BME CSR_BIT(18)
#define FBNIC_RPC_TCAM_ACT0_IPSRC_VALID CSR_BIT(3)
#define FBNIC_RPC_TCAM_ACT0_IPDST_VALID CSR_BIT(7)
#define FBNIC_RPC_TCAM_ACT0_OUTER_IPSRC_VALID CSR_BIT(11)
#define FBNIC_RPC_TCAM_ACT0_OUTER_IPDST_VALID CSR_BIT(15)
#define FBNIC_RPC_TCAM_ACT1_L2_MACDA_VALID CSR_BIT(10)
#define FBNIC_RPC_TCAM_ACT1_IP_IS_V6 CSR_BIT(11)
#define FBNIC_RPC_TCAM_ACT1_IP_VALID CSR_BIT(12)
#define FBNIC_RPC_TCAM_ACT1_OUTER_IP_VALID CSR_BIT(13)
#define FBNIC_RPC_TCAM_ACT1_L4_IS_UDP CSR_BIT(14)
#define FBNIC_RPC_TCAM_ACT1_L4_VALID CSR_BIT(15)