tegra_clk_register_periph_gate
clk = tegra_clk_register_periph_gate(data->gate_name,
clk = tegra_clk_register_periph_gate(data->name,
clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
clk = tegra_clk_register_periph_gate("csus", "vi_sensor", 0,
clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler",
clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
clk = tegra_clk_register_periph_gate("dsi", "pll_d_out0", 0,
clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,
clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0,
clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0,
clk = tegra_clk_register_periph_gate("csus", "csus_mux", 0,
clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
clk = tegra_clk_register_periph_gate("csus", "vi_sensor", 0,
clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
struct clk *tegra_clk_register_periph_gate(const char *name,