CSR7
iowrite32(tulip_tbl[tp->chip_id].valid_intrs, tp->base_addr+CSR7);
iowrite32(tulip_tbl[tp->chip_id].valid_intrs&~RxPollInt, ioaddr + CSR7);
iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
iowrite32(0x00, ioaddr + CSR7);
iowrite32(((~csr5) & 0x0001ebef) | AbnormalIntr | TimerInt, ioaddr + CSR7);
iowrite32(0x00, ioaddr + CSR7);
ioaddr + CSR7);
if(!ioread32(ioaddr + CSR7)) {
iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
iowrite32((ioread32(ioaddr + CSR7) & ~TPLnkFail) | TPLnkPass, ioaddr + CSR7);
iowrite32((ioread32(ioaddr + CSR7) & ~TPLnkPass) | TPLnkFail, ioaddr + CSR7);
if(!ioread32(ioaddr + CSR7)) {
iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
(int)ioread32(ioaddr + CSR7),
iowrite32 (0x00000000, ioaddr + CSR7);
val = xr32(CSR7); /* Interrupt enable register */
xw32(CSR7, val);
val = xr32(CSR7); /* Interrupt enable register */
xw32(CSR7, val);
val = xr32(CSR7); /* Interrupt enable register */
xw32(CSR7, val);
xw32(CSR7, 0);
val = xr32(CSR7); /* Interrupt enable register */
xw32(CSR7, val);
reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
rt2x00mmio_register_write(rt2x00dev, CSR7, reg);