CSR3
lance->RAP = CSR3; /* Interrupt Masks and Deferral Control */
REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0);
REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0);
REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0);
val = lp->a->read_csr(ioaddr, CSR3);
lp->a->write_csr(ioaddr, CSR3, val);
val = lp->a->read_csr(ioaddr, CSR3);
lp->a->write_csr(ioaddr, CSR3, val);
val = lp->a->read_csr(ioaddr, CSR3);
lp->a->write_csr(ioaddr, CSR3, val);
val = lp->a->read_csr(ioaddr, CSR3);
lp->a->write_csr(ioaddr, CSR3, val);
REGA(CSR3) = CSR3_BSWP | CSR3_ACON | CSR3_BCON;
REGA(CSR3) = CSR3_BSWP;
REGA(CSR3) = CSR3_BSWP;
REGA(CSR3) = CSR3_BSWP;
REGA(CSR3) = CSR3_BSWP;
REGA( CSR3 ) = CSR3_BSWP;
iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
xw32(CSR3, address); /* Receive descr list address */
xw32(CSR3, val); /* Receive descriptor address */
rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,