CSR1
pd->regs + CSR1);
FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
ipd->regs + CSR1);
FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
REGA( CSR1 ) = 0;
REGA(CSR1) = dvma_vtob(&(MEM->init));
iowrite32(0, ioaddr + CSR1);
iowrite32(0, ioaddr + CSR1);
iowrite32(0, ioaddr + CSR1);
iowrite32(0, tp->base_addr + CSR1);
xw32(CSR1, 0);
ret = ravb_endisable_csum_gbeth(ndev, CSR1, val, CSR0_TPE);
ravb_write(ndev, CSR1_CSUM_ENABLE, CSR1);
reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
rt2x00mmio_register_write(rt2x00dev, CSR1, reg);