CSR0
lance->RAP = CSR0; /* PCnet-ISA Controller Status */
lance->RAP = CSR0; /* PCnet-ISA Controller Status */
lance->RAP = CSR0; /* PCnet-ISA Controller Status */
lance->RAP = CSR0; /* PCnet-ISA Controller Status */
lance->RAP = CSR0; /* PCnet-ISA Controller Status */
lance->RAP = CSR0; /* PCnet-ISA Controller Status */
lance->RAP = CSR0; /* PCnet-ISA Controller Status */
lance->RAP = CSR0; /* PCnet-ISA Controller Status */
lance->RAP = CSR0; /* PCnet-ISA Controller Status */
lance->RAP = CSR0; /* PCnet-ISA Controller Status */
AREG = CSR0;
REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT;
ioaddr[1] = CSR0;
REGA( CSR0 ) = CSR0_STOP;
REGA( CSR0 ) = CSR0_INIT;
AREG = CSR0;
REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT;
AREG = CSR0;
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
lp->a->write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN);
csr0 = a->read_csr(ioaddr, CSR0);
a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL);
lp->a->read_csr(ioaddr, CSR0));
if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP)
lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
lp->a->write_csr(ioaddr, CSR0, csr0_bits);
dev->name, lp->a->read_csr(ioaddr, CSR0));
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
__func__, lp->a->read_csr(ioaddr, CSR0));
lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
csr0 = lp->a->read_csr(ioaddr, CSR0);
lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f);
csr0, lp->a->read_csr(ioaddr, CSR0));
csr0 = lp->a->read_csr(ioaddr, CSR0);
lp->a->read_csr(ioaddr, CSR0));
lp->a->read_csr(ioaddr, CSR0));
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
ioaddr_probe[1] = CSR0;
REGA(CSR0) = CSR0_STOP;
REGA(CSR0) = CSR0_STOP;
REGA(CSR0) = CSR0_INIT;
REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT;
AREG = CSR0;
REGA( CSR0 ) = CSR0_STOP;
REGA( CSR0 ) = CSR0_INIT | CSR0_STRT;
REGA(CSR0) = CSR0_INEA | CSR0_TDMD | CSR0_STRT;
AREG = CSR0;
AREG = CSR0;
REGA(CSR0) = CSR0_STOP;
REGA(CSR0) = CSR0_STRT | CSR0_INEA;
REGA(CSR0) = CSR0_STOP;
REGA(CSR0) = CSR0_STRT | CSR0_INEA;
REGA(CSR0) = CSR0_INEA;
AREG = CSR0;
REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT;
iowrite32(0x00000001, ioaddr + CSR0);
iowrite32(tp->csr0, ioaddr + CSR0);
ioread32(ioaddr + CSR0),
val = xr32(CSR0);
xw32(CSR0, val);
val = xr32(CSR0);
xw32(CSR0, val);
xw32(CSR0, val);
ravb_write(ndev, csr0 & ~mask, CSR0);
ret = ravb_wait(ndev, CSR0, mask, 0);
ravb_write(ndev, csr0, CSR0);
ravb_write(ndev, 0, CSR0);
if (ravb_wait(ndev, CSR0, CSR0_TPE | CSR0_RPE, 0)) {
ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0);
reg = rt2x00mmio_register_read(rt2x00dev, CSR0);
reg = rt2x00mmio_register_read(rt2x00dev, CSR0);
spi_writel(as, CSR0 + 4 * chip_select, csr);
csr = spi_readl(as, CSR0 + 4 * chip_select);
spi_writel(as, CSR0 + 4 * chip_select, csr);
spi_writel(as, CSR0 + 4 * chip_select, asd->csr);
spi_writel(as, CSR0, asd->csr);
csr = spi_readl(as, CSR0 + 4 * i);
spi_writel(as, CSR0 + 4 * i,
csr = spi_readl(as, CSR0 + 4 * chip_select);
spi_writel(as, CSR0 + 4 * chip_select, csr);